Buffering global interconnects in structured ASIC design

Tianpei Zhang; Sachin S Sapatnekar

Buffering global interconnects in structured ASIC design

Tianpei Zhang, Sachin S Sapatnekar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Scopus citations

Abstract

Structured ASICs present an attractive alternative to reducing de-sign costs and turnaround times in nanometer designs. As with conven-tional ASICs, such designs require global wires to be buffered. However, via-programmable designs must prefabricate and preplace buffers in the layout. This oaper proposes a novel and accurate statistical estimation technique jo. distributing prefabricated buffers through a layout. It employs Rent's rule to estimate the buffer distribution required for the layout, so that an appropriate structured ASIC may be selected for the design. Experimental results show that the estimation for a uniform buffer distribution is accurate and economic.

Original language	English (US)
Title of host publication	Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Pages	23-26
Number of pages	4
State	Published - 2005
Event	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China Duration: Jan 18 2005 → Jan 21 2005

Publication series

Name	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
Volume	1

Other

Other	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
Country/Territory	China
City	Shanghai
Period	1/18/05 → 1/21/05

Bibliographical note

Funding Information:
This research is partly supported by NSF award CCF-0205227.

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Buffering global interconnects in structured ASIC design. / Zhang, Tianpei; Sapatnekar, Sachin S.
Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. 2005. p. 23-26 1466123 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhang, T & Sapatnekar, SS 2005, Buffering global interconnects in structured ASIC design. in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005., 1466123, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 1, pp. 23-26, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 1/18/05.

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Buffering global interconnects in structured ASIC design

Abstract

Publication series

Other

Bibliographical note

OpenUrl availability

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