The use of variable and multiple power supplies to reduce overall power consumption for digital circuits and the need for separate power supplies for mixed analog-digital circuits have been well documented. High efficiency capacitive voltage multipliers can be used to generate multiple and variable on-chip power supplies. Previous literature has presented individual capacitive voltage multiplier designs but has not presented an overview of the design space (i.e., the complete topology list) nor have they provided a method for selecting the best topology for each application. In this paper we identify a complete family of capacitive voltage multiplier modes. We then trim the complete list to a list of recommended modes using a set of heuristic rules. Six of these recommended modes are new and have not appealed in previous literature. We also develop a general set of performance equations for capacitive voltage multipliers that allows us to select and design the best topology for any particular application. We review the effects of parasitic resistance and capacitance and develop new simplified methods to approximate the impact of parasitic capacitances. To verify the validity of our design equations we fabricated and tested a set of sample designs. There is extremely good matching between measured and predicted performance. All the capacitive voltage multipliers modes developed in this paper have either better or as good as the performance of previously presented designs.