Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

K. Rim; J. Chu; H. Chen; K. A. Jenkins; T. Kanarsky; K. Lee; A. Mocuta; H. Zhu; R. Roy; J. Newbury; J. Ott; K. Petrarca; P. Mooney; D. Lacey; S. Koester; K. Chan; D. Boyd; M. Ieong; H. S. Wong

Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

K. Rim, J. Chu, H. Chen, K. A. Jenkins, T. Kanarsky, K. Lee, A. Mocuta, H. Zhu, R. Roy, J. Newbury, J. Ott, K. Petrarca, P. Mooney, D. Lacey, S. Koester, K. Chan, D. Boyd, M. Ieong, H. S. Wong

Electrical and Computer Engineering

Research output: Contribution to conference › Paper › peer-review

188 Scopus citations

Abstract

The device design and characteristics of sub-100 nm strained Si N- and PMOSFETs were discussed. A enhancement of 110% was observed in the strained Si devices with 1.2% tensile strain, along with a 45% increase in the peak hole mobility. A comparison of current-voltage characteristics of 100 nm PFETs was done. The strained Si (SS) PFETs showed comparable subthreshold characteristics while showing higher current drive.

Original language	English (US)
Pages	98-99
Number of pages	2
State	Published - 2002
Event	2002 Symposium on VLSI Technology Digest of Technical Papers - Honolulu, HI, United States Duration: Jun 11 2002 → Jun 13 2002

Other

Other	2002 Symposium on VLSI Technology Digest of Technical Papers
Country/Territory	United States
City	Honolulu, HI
Period	6/11/02 → 6/13/02

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Rim, K., Chu, J., Chen, H., Jenkins, K. A., Kanarsky, T., Lee, K., Mocuta, A., Zhu, H., Roy, R., Newbury, J., Ott, J., Petrarca, K., Mooney, P., Lacey, D., Koester, S., Chan, K., Boyd, D., Ieong, M., & Wong, H. S. (2002). Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs. 98-99. Paper presented at 2002 Symposium on VLSI Technology Digest of Technical Papers, Honolulu, HI, United States.

Rim, K, Chu, J, Chen, H, Jenkins, KA, Kanarsky, T, Lee, K, Mocuta, A, Zhu, H, Roy, R, Newbury, J, Ott, J, Petrarca, K, Mooney, P, Lacey, D, Koester, S, Chan, K, Boyd, D, Ieong, M & Wong, HS 2002, 'Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs', Paper presented at 2002 Symposium on VLSI Technology Digest of Technical Papers, Honolulu, HI, United States, 6/11/02 - 6/13/02 pp. 98-99.

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abstract = "The device design and characteristics of sub-100 nm strained Si N- and PMOSFETs were discussed. A enhancement of 110% was observed in the strained Si devices with 1.2% tensile strain, along with a 45% increase in the peak hole mobility. A comparison of current-voltage characteristics of 100 nm PFETs was done. The strained Si (SS) PFETs showed comparable subthreshold characteristics while showing higher current drive.",

author = "K. Rim and J. Chu and H. Chen and Jenkins, {K. A.} and T. Kanarsky and K. Lee and A. Mocuta and H. Zhu and R. Roy and J. Newbury and J. Ott and K. Petrarca and P. Mooney and D. Lacey and S. Koester and K. Chan and D. Boyd and M. Ieong and Wong, {H. S.}",

year = "2002",

language = "English (US)",

pages = "98--99",

note = "2002 Symposium on VLSI Technology Digest of Technical Papers ; Conference date: 11-06-2002 Through 13-06-2002",

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TY - CONF

T1 - Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

AU - Rim, K.

AU - Chu, J.

AU - Chen, H.

AU - Jenkins, K. A.

AU - Kanarsky, T.

AU - Lee, K.

AU - Mocuta, A.

AU - Zhu, H.

AU - Roy, R.

AU - Newbury, J.

AU - Ott, J.

AU - Petrarca, K.

AU - Mooney, P.

AU - Lacey, D.

AU - Koester, S.

AU - Chan, K.

AU - Boyd, D.

AU - Ieong, M.

AU - Wong, H. S.

PY - 2002

Y1 - 2002

N2 - The device design and characteristics of sub-100 nm strained Si N- and PMOSFETs were discussed. A enhancement of 110% was observed in the strained Si devices with 1.2% tensile strain, along with a 45% increase in the peak hole mobility. A comparison of current-voltage characteristics of 100 nm PFETs was done. The strained Si (SS) PFETs showed comparable subthreshold characteristics while showing higher current drive.

AB - The device design and characteristics of sub-100 nm strained Si N- and PMOSFETs were discussed. A enhancement of 110% was observed in the strained Si devices with 1.2% tensile strain, along with a 45% increase in the peak hole mobility. A comparison of current-voltage characteristics of 100 nm PFETs was done. The strained Si (SS) PFETs showed comparable subthreshold characteristics while showing higher current drive.

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UR - http://www.scopus.com/inward/citedby.url?scp=0036045608&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0036045608

SP - 98

EP - 99

T2 - 2002 Symposium on VLSI Technology Digest of Technical Papers

Y2 - 11 June 2002 through 13 June 2002

ER -

Characteristics and device design of sub-100 nm strained Si N- and PMOSFETs

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