Charge trapping analysis in sputtered BixSe1-x based accumulation-mode FETs

Protyush Sahu, Junyang Chen, Jian Ping Wang

Research output: Contribution to journalArticlepeer-review

Abstract

Topological materials have attracted a lot of attention in the field of beyond Complementary Metal Oxide Semiconductor (CMOS) devices. Topological Insulators (TI) have been proposed for future high electron mobility field effect transistor (FET) devices that make the physics of operation and especially the oxide-film interface extremely crucial to understand. The effects of the gate voltage on the charge trapping in TI-based FET devices are reported in this work. Sputtered BixSe1-x was chosen as the TI material. The interfacial chemistry was characterized using X-ray photoelectron spectroscopy (XPS), which shows a presence of Mg2+ and oxygen impurities. A unique hysteresis behavior was found for the gate transfer characteristics, with respect to the gate voltage. This was attributed to the charge trapping in the gate oxide and across the SiO2/BixSe1-x interface. We simulated the effects of charge fluctuations on the resistivity of the film. These devices operate under accumulation mode rather inversion mode. Application of positive gate voltage results in accumulation of electrons in the "n-type" BixSe1-x layer resulting in an increase of conductivity. In order to explain the drain current-gate voltage behavior, we used a simple polynomial model to describe the change in the device characteristics due to charge traps. The model was fitted with our experimental results. We further analyzed the gate leakage current, which showed a good match with trap-assisted tunneling (TAT) process that was used to derive trap parameters. The obtained trap parameters show the presence of ultra-deep charge traps contributing to the hysteretic behavior.

Original languageEnglish (US)
Article number015315
JournalAIP Advances
Volume10
Issue number1
DOIs
StatePublished - Jan 1 2020

Bibliographical note

Funding Information:
This work was in part supported by ASCENT, one of the six centers of JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA under University of Minnesota grant no. 3014-11128-00065667. Portions of this work were carried out in the Minnesota Nano Center, which is supported by the National Science Foundation (NSF) through the National Nano Coordinated Infrastructure, under Award Number ECCS-1542202. Parts of this work were carried out at Characterization facility, University of Minnesota, which receives partial support from NSF through the MRSEC program, under Award Number DMR-1420013.

How much support was provided by MRSEC?

  • Shared

Reporting period for MRSEC

  • Period 7

Fingerprint Dive into the research topics of 'Charge trapping analysis in sputtered Bi<sub>x</sub>Se<sub>1-x</sub> based accumulation-mode FETs'. Together they form a unique fingerprint.

Cite this