Chopper stabilized sub 1V reference voltage in 65nm CMOS

Rakesh Kumar Palani; Aravindhan Rangarajan; Ramesh Harjani

doi:10.1109/MWSCAS.2015.7282081

Chopper stabilized sub 1V reference voltage in 65nm CMOS

Rakesh Kumar Palani, Aravindhan Rangarajan, Ramesh Harjani

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

A sub 1V reference circuit is proposed, that exploits the CTAT and PTAT voltages in the beta multiplier circuit to attain a stable voltage with temperature and power supply. A one-time calibration is integrated in the architecture to get a good performance over process. Further, chopper stabilization is proposed in the circuit itself rather than in the OTA to acheive a 4.8x reduction in integrated flicker noise voltage without increasing power dissipation. The prototype designed in TSMC's 65nm general purpose CMOS for 236mV nominal voltage, shows a temperature coefficient of 18 ppm/°C from -40 to 100°C with a power supply ranging from 0.8 to 2V while consuming 16μA current. Simulated variation in the reference voltage is 0.7mV with power supply at nominal temperature.

Original language	English (US)
Title of host publication	IEEE 58th International Midwest Symposium on Circuits and Systems
Subtitle of host publication	Climbing to New Heights, MWSCAS 2015 - Conference Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781467365574
DOIs	https://doi.org/10.1109/MWSCAS.2015.7282081
State	Published - Sep 28 2015
Event	58th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2015 - Fort Collins, United States Duration: Aug 2 2015 → Aug 5 2015

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	2015-September
ISSN (Print)	1548-3746

Other

Other	58th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2015
Country/Territory	United States
City	Fort Collins
Period	8/2/15 → 8/5/15

Keywords

CMOS
subbandgap reference voltage circuit
temperature sensitivity

Access

10.1109/MWSCAS.2015.7282081

OpenUrl availability

Full text

Cite this

Palani, R. K., Rangarajan, A., & Harjani, R. (2015). Chopper stabilized sub 1V reference voltage in 65nm CMOS. In IEEE 58th International Midwest Symposium on Circuits and Systems: Climbing to New Heights, MWSCAS 2015 - Conference Proceedings Article 7282081 (Midwest Symposium on Circuits and Systems; Vol. 2015-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS.2015.7282081

Chopper stabilized sub 1V reference voltage in 65nm CMOS. / Palani, Rakesh Kumar; Rangarajan, Aravindhan; Harjani, Ramesh.
IEEE 58th International Midwest Symposium on Circuits and Systems: Climbing to New Heights, MWSCAS 2015 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc., 2015. 7282081 (Midwest Symposium on Circuits and Systems; Vol. 2015-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Palani, RK, Rangarajan, A & Harjani, R 2015, Chopper stabilized sub 1V reference voltage in 65nm CMOS. in IEEE 58th International Midwest Symposium on Circuits and Systems: Climbing to New Heights, MWSCAS 2015 - Conference Proceedings., 7282081, Midwest Symposium on Circuits and Systems, vol. 2015-September, Institute of Electrical and Electronics Engineers Inc., 58th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2015, Fort Collins, United States, 8/2/15. https://doi.org/10.1109/MWSCAS.2015.7282081

Palani RK, Rangarajan A, Harjani R. Chopper stabilized sub 1V reference voltage in 65nm CMOS. In IEEE 58th International Midwest Symposium on Circuits and Systems: Climbing to New Heights, MWSCAS 2015 - Conference Proceedings. Institute of Electrical and Electronics Engineers Inc. 2015. 7282081. (Midwest Symposium on Circuits and Systems). doi: 10.1109/MWSCAS.2015.7282081

@inproceedings{689b35392a6b4ed3b65eb0fdb31bc8c8,

title = "Chopper stabilized sub 1V reference voltage in 65nm CMOS",

abstract = "A sub 1V reference circuit is proposed, that exploits the CTAT and PTAT voltages in the beta multiplier circuit to attain a stable voltage with temperature and power supply. A one-time calibration is integrated in the architecture to get a good performance over process. Further, chopper stabilization is proposed in the circuit itself rather than in the OTA to acheive a 4.8x reduction in integrated flicker noise voltage without increasing power dissipation. The prototype designed in TSMC's 65nm general purpose CMOS for 236mV nominal voltage, shows a temperature coefficient of 18 ppm/°C from -40 to 100°C with a power supply ranging from 0.8 to 2V while consuming 16μA current. Simulated variation in the reference voltage is 0.7mV with power supply at nominal temperature.",

keywords = "CMOS, subbandgap reference voltage circuit, temperature sensitivity",

author = "Palani, {Rakesh Kumar} and Aravindhan Rangarajan and Ramesh Harjani",

year = "2015",

month = sep,

day = "28",

doi = "10.1109/MWSCAS.2015.7282081",

language = "English (US)",

series = "Midwest Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "IEEE 58th International Midwest Symposium on Circuits and Systems",

note = "58th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2015 ; Conference date: 02-08-2015 Through 05-08-2015",

}

TY - GEN

T1 - Chopper stabilized sub 1V reference voltage in 65nm CMOS

AU - Palani, Rakesh Kumar

AU - Rangarajan, Aravindhan

AU - Harjani, Ramesh

PY - 2015/9/28

Y1 - 2015/9/28

N2 - A sub 1V reference circuit is proposed, that exploits the CTAT and PTAT voltages in the beta multiplier circuit to attain a stable voltage with temperature and power supply. A one-time calibration is integrated in the architecture to get a good performance over process. Further, chopper stabilization is proposed in the circuit itself rather than in the OTA to acheive a 4.8x reduction in integrated flicker noise voltage without increasing power dissipation. The prototype designed in TSMC's 65nm general purpose CMOS for 236mV nominal voltage, shows a temperature coefficient of 18 ppm/°C from -40 to 100°C with a power supply ranging from 0.8 to 2V while consuming 16μA current. Simulated variation in the reference voltage is 0.7mV with power supply at nominal temperature.

AB - A sub 1V reference circuit is proposed, that exploits the CTAT and PTAT voltages in the beta multiplier circuit to attain a stable voltage with temperature and power supply. A one-time calibration is integrated in the architecture to get a good performance over process. Further, chopper stabilization is proposed in the circuit itself rather than in the OTA to acheive a 4.8x reduction in integrated flicker noise voltage without increasing power dissipation. The prototype designed in TSMC's 65nm general purpose CMOS for 236mV nominal voltage, shows a temperature coefficient of 18 ppm/°C from -40 to 100°C with a power supply ranging from 0.8 to 2V while consuming 16μA current. Simulated variation in the reference voltage is 0.7mV with power supply at nominal temperature.

KW - CMOS

KW - subbandgap reference voltage circuit

KW - temperature sensitivity

UR - http://www.scopus.com/inward/record.url?scp=84962074333&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84962074333&partnerID=8YFLogxK

U2 - 10.1109/MWSCAS.2015.7282081

DO - 10.1109/MWSCAS.2015.7282081

M3 - Conference contribution

AN - SCOPUS:84962074333

T3 - Midwest Symposium on Circuits and Systems

BT - IEEE 58th International Midwest Symposium on Circuits and Systems

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 58th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2015

Y2 - 2 August 2015 through 5 August 2015

ER -

Chopper stabilized sub 1V reference voltage in 65nm CMOS

Abstract

Publication series

Other

Keywords

Access

OpenUrl availability

Other files and links

Fingerprint

Cite this