Abstract
Recent publications have shown that clock jitter can improve timing margin through the compensation effect between the clock cycle and the datapath delay under the influence of resonant supply noise. This paper presents a comprehensive study of this beneficial clock-data compensation effect including an analysis of its dependency on various design parameters and a new phase-shifted clock buffer design that can enhance the effect. Measurement result from a 1.2 V, 65 nm test chip shows an 8-27% increase in the maximum operating frequency while saving 85% of the clock buffer area compared to prior art. An accurate timing model is derived to estimate the beneficial jitter effect.
| Original language | English (US) |
|---|---|
| Article number | 5584967 |
| Pages (from-to) | 2130-2141 |
| Number of pages | 12 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 45 |
| Issue number | 10 |
| DOIs | |
| State | Published - Oct 2010 |
Bibliographical note
Funding Information:Manuscript received November 22, 2009; revised May 09, 2010; accepted July 15, 2010. Date of current version September 24, 2010. This paper was approved by Associate Editor Stephan Rusu. This work was supported in part by the Semiconductor Research Corporation under award 2008-HJ-1804. D. Jiao and C. H. Kim are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: dong@umn.edu). J. Gu is with the MaxLinear Incorporated, Carlsbad, CA 92011 USA. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2010.2063931 Fig. 1. Measured supply network impedance response of Intel’s Nehalem microprocessor [15].
Keywords
- Clock-data compensation
- clock distribution
- resonant noise
- supply noise