Circuit techniques for enhancing the clock data compensation effect under resonant supply noise

Recent publications have shown that clock jitter can improve timing margin through the compensation effect between the clock cycle and the datapath delay under the influence of resonant supply noise. In this paper, novel phase-shifted clock buffer designs are proposed to enhance this "beneficial jitter effect". Compared with existing designs, our design saves 85% of the clock buffer area while achieving a similar 10% increase in the maximum operating frequency for typical pipeline circuits. Measurement results are presented from a test chip implemented in a 1.2V, 65nm process.