Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs

Won Ho Choi; Hoonki Kim; Chris H. Kim

doi:10.1109/CICC.2015.7338417

Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs

Won Ho Choi, Hoonki Kim, Chris H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

Stress equalization and stress removal techniques for mitigating short-term Vth instability issues in SAR ADCs have been experimentally verified using an 80kS/s 10-bit differential SAR ADC fabricated in a 65nm LP CMOS process. The proposed techniques are particularly effective in enhancing the performance of high resolution and low sample rate SAR ADCs which are known to be more susceptible to short-term Vth degradation and recovery effects induced by Bias Temperature Instability (BTI). Experimental data shows that the proposed techniques can reduce the worst case DNL by 0.90 LSB and 0.77 LSB, respectively, compared to a typical SAR ADC.

Original language	English (US)
Title of host publication	2015 IEEE Custom Integrated Circuits Conference, CICC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479986828
DOIs	https://doi.org/10.1109/CICC.2015.7338417
State	Published - Nov 25 2015
Event	IEEE Custom Integrated Circuits Conference, CICC 2015 - San Jose, United States Duration: Sep 28 2015 → Sep 30 2015

Publication series

Name	Proceedings of the Custom Integrated Circuits Conference
Volume	2015-November
ISSN (Print)	0886-5930

Other

Other	IEEE Custom Integrated Circuits Conference, CICC 2015
Country/Territory	United States
City	San Jose
Period	9/28/15 → 9/30/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Keywords

Short-term Vth instability
aging
analog circuit reliability
bias temperature instability
mitigation technique
successive approximation register analog-to-digital converter

Access

10.1109/CICC.2015.7338417

OpenUrl availability

Full text

Cite this

Choi, W. H., Kim, H., & Kim, C. H. (2015). Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs. In 2015 IEEE Custom Integrated Circuits Conference, CICC 2015 Article 7338417 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2015-November). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2015.7338417

Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs. / Choi, Won Ho; Kim, Hoonki; Kim, Chris H.
2015 IEEE Custom Integrated Circuits Conference, CICC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7338417 (Proceedings of the Custom Integrated Circuits Conference; Vol. 2015-November).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Choi, WH, Kim, H & Kim, CH 2015, Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs. in 2015 IEEE Custom Integrated Circuits Conference, CICC 2015., 7338417, Proceedings of the Custom Integrated Circuits Conference, vol. 2015-November, Institute of Electrical and Electronics Engineers Inc., IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, United States, 9/28/15. https://doi.org/10.1109/CICC.2015.7338417

@inproceedings{beefc36cc8d84c268d6f49448512348c,

title = "Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs",

abstract = "Stress equalization and stress removal techniques for mitigating short-term Vth instability issues in SAR ADCs have been experimentally verified using an 80kS/s 10-bit differential SAR ADC fabricated in a 65nm LP CMOS process. The proposed techniques are particularly effective in enhancing the performance of high resolution and low sample rate SAR ADCs which are known to be more susceptible to short-term Vth degradation and recovery effects induced by Bias Temperature Instability (BTI). Experimental data shows that the proposed techniques can reduce the worst case DNL by 0.90 LSB and 0.77 LSB, respectively, compared to a typical SAR ADC.",

keywords = "Short-term Vth instability, aging, analog circuit reliability, bias temperature instability, mitigation technique, successive approximation register analog-to-digital converter",

author = "Choi, {Won Ho} and Hoonki Kim and Kim, {Chris H.}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE Custom Integrated Circuits Conference, CICC 2015 ; Conference date: 28-09-2015 Through 30-09-2015",

year = "2015",

month = nov,

day = "25",

doi = "10.1109/CICC.2015.7338417",

language = "English (US)",

series = "Proceedings of the Custom Integrated Circuits Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2015 IEEE Custom Integrated Circuits Conference, CICC 2015",

}

TY - GEN

T1 - Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs

AU - Choi, Won Ho

AU - Kim, Hoonki

AU - Kim, Chris H.

PY - 2015/11/25

Y1 - 2015/11/25

N2 - Stress equalization and stress removal techniques for mitigating short-term Vth instability issues in SAR ADCs have been experimentally verified using an 80kS/s 10-bit differential SAR ADC fabricated in a 65nm LP CMOS process. The proposed techniques are particularly effective in enhancing the performance of high resolution and low sample rate SAR ADCs which are known to be more susceptible to short-term Vth degradation and recovery effects induced by Bias Temperature Instability (BTI). Experimental data shows that the proposed techniques can reduce the worst case DNL by 0.90 LSB and 0.77 LSB, respectively, compared to a typical SAR ADC.

AB - Stress equalization and stress removal techniques for mitigating short-term Vth instability issues in SAR ADCs have been experimentally verified using an 80kS/s 10-bit differential SAR ADC fabricated in a 65nm LP CMOS process. The proposed techniques are particularly effective in enhancing the performance of high resolution and low sample rate SAR ADCs which are known to be more susceptible to short-term Vth degradation and recovery effects induced by Bias Temperature Instability (BTI). Experimental data shows that the proposed techniques can reduce the worst case DNL by 0.90 LSB and 0.77 LSB, respectively, compared to a typical SAR ADC.

KW - Short-term Vth instability

KW - aging

KW - analog circuit reliability

KW - bias temperature instability

KW - mitigation technique

KW - successive approximation register analog-to-digital converter

UR - http://www.scopus.com/inward/record.url?scp=84959186720&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84959186720&partnerID=8YFLogxK

U2 - 10.1109/CICC.2015.7338417

DO - 10.1109/CICC.2015.7338417

M3 - Conference contribution

AN - SCOPUS:84959186720

T3 - Proceedings of the Custom Integrated Circuits Conference

BT - 2015 IEEE Custom Integrated Circuits Conference, CICC 2015

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE Custom Integrated Circuits Conference, CICC 2015

Y2 - 28 September 2015 through 30 September 2015

ER -

Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs

Abstract

Publication series

Other

Bibliographical note

Keywords

Access

OpenUrl availability

Other files and links

Fingerprint

Cite this