Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs

Won Ho Choi, Hoonki Kim, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Scopus citations

Abstract

Stress equalization and stress removal techniques for mitigating short-term Vth instability issues in SAR ADCs have been experimentally verified using an 80kS/s 10-bit differential SAR ADC fabricated in a 65nm LP CMOS process. The proposed techniques are particularly effective in enhancing the performance of high resolution and low sample rate SAR ADCs which are known to be more susceptible to short-term Vth degradation and recovery effects induced by Bias Temperature Instability (BTI). Experimental data shows that the proposed techniques can reduce the worst case DNL by 0.90 LSB and 0.77 LSB, respectively, compared to a typical SAR ADC.

Original languageEnglish (US)
Title of host publication2015 IEEE Custom Integrated Circuits Conference, CICC 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Volume2015-November
ISBN (Electronic)9781479986828
DOIs
StatePublished - Nov 25 2015
EventIEEE Custom Integrated Circuits Conference, CICC 2015 - San Jose, United States
Duration: Sep 28 2015Sep 30 2015

Other

OtherIEEE Custom Integrated Circuits Conference, CICC 2015
CountryUnited States
CitySan Jose
Period9/28/159/30/15

Keywords

  • aging
  • analog circuit reliability
  • bias temperature instability
  • mitigation technique
  • Short-term Vth instability
  • successive approximation register analog-to-digital converter

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