A novel clock and data recovery architecture with adaptive loop gain is proposed for spread spectrum SerDes applications such as the Serial AT Attachment. The proposed design consists of a half-rate Alexander phase detector, a phase-shifting phase interpolator with a frequency differentiator and an adaptive loop gain filter. The frequency differentiator determines the clock rate difference between the referenced clock and the recovered clock. This value is then used to adjust the gain of the adaptive loop filter for better acquisition of lock with minimized jitter. The proposed design can be implemented in a digital CMOS process which reduces the design difficulty and cost. The system operation has been verified using the Cadence SpectreRF and Verilog-A simulators. The results show that the system is capable of recovering a ±5000 ppm spread spectrum data with up to a maximum of 0.5 UI of deterministic jitter.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|State||Published - Dec 1 2005|
|Event||IEEE International Symposium on Circuits and Systems 2005, ISCAS 2005 - Kobe, Japan|
Duration: May 23 2005 → May 26 2005