TY - JOUR
T1 - Clock tree synthesis for multi-chip modules
AU - Lehther, Daksh
AU - Sapatnekar, Sachin S.
PY - 1996/12/1
Y1 - 1996/12/1
N2 - While designing interconnect for MCM's, one must take into consideration the distributed RLC effects, due to which signals may display nonmonotonic behavior and substantial ringing. This paper considers the problem of designing clock trees for MCM's. A fully distributed RLC model is utilized for AWE-based analysis and synthesis, and appropriate measures are taken to ensure adequate signal damping and for buffer insertion to satisfy constraints on the clock signal slew rate. Experimental results, verified by SPICE simulations, show that this method can be used to build clock trees with near-zero skews.
AB - While designing interconnect for MCM's, one must take into consideration the distributed RLC effects, due to which signals may display nonmonotonic behavior and substantial ringing. This paper considers the problem of designing clock trees for MCM's. A fully distributed RLC model is utilized for AWE-based analysis and synthesis, and appropriate measures are taken to ensure adequate signal damping and for buffer insertion to satisfy constraints on the clock signal slew rate. Experimental results, verified by SPICE simulations, show that this method can be used to build clock trees with near-zero skews.
UR - http://www.scopus.com/inward/record.url?scp=0030421299&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=0030421299&partnerID=8YFLogxK
M3 - Article
AN - SCOPUS:0030421299
SN - 1092-3152
SP - 50
EP - 53
JO - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
JF - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
ER -