CMOS switched-op-amp-based sample-and-hold circuit

This paper presents a sample-and-hold design that is based on a switched-op-amp topology. Charge injection errors are greatly reduced by turning off transistors in the saturation region instead of the triode region as is the case for traditional MOS switches. The remaining clock feedthrough error is mostly signal-independent and is cancelled out by a pseudodifferential topology. Switched-op-amps are designed and fabricated in a 2-μ CMOS technology. The measurement results show that the harmonics are at least 78 dB below the signal level. Both the measurement results from fabricated IC's and simulation results suggest the potential benefits of this approach in comparison to traditional switched-capacitor circuits.