Comparing simulation techniques for microarchitecture-aware floorplanning

Vidyasagar Nookala, Ying Chen, David J Lilja, Sachin S Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

Due to the long simulation times of the reference input sets, microarchitects resort to alternative techniques to speed up cycle-accurate simulations. However, the reduction in the runtimes comes with an associated loss of accuracy in replicating the characteristics of the reference sets. In addition, the effect of these inaccuracies on the overall performance can vary across different microarchitecture optimizations or enhancements. In this work, we study and compare two such techniques, reduced input sets and statistical sampling, in the context of microarchitecture-aware floorplanning, a physical design stage, where the objective is to find an IPC-optimal global placement of the blocks of a microprocessor. The variation in the IPC results due the insertion of additional flip-flops on some across-chip wires of the processor that have multicycle delays in nanometer technology nodes. The objective of IPC-aware floorplanning is to minimize the amount of pipelining required by the system buses that are critical in determining the system performance. Our results indicate that, although the two techniques exhibit contrasting behavior in quantifying the criticality of bus latencies, the ensuing floorplanning optimization process results in almost identical performance improvements for both reduced input sets and sampling. The reason behind this is that, for discrete optimization problems such as IPC-aware floorplanning, a reasonably accurate relative ordering of performance bottlenecks is sufficient, absolute accuracy is not necessary.

Original languageEnglish (US)
Title of host publicationISPASS 2006
Subtitle of host publicationIEEE International Symposium on Performance Analysis of Systems and Software, 2006
Pages80-88
Number of pages9
Volume2006
StatePublished - Nov 14 2006
EventISPASS 2006: IEEE International Symposium on Performance Analysis of Systems and Software, 2006 - Austin, TX, United States
Duration: Mar 19 2006Mar 21 2006

Other

OtherISPASS 2006: IEEE International Symposium on Performance Analysis of Systems and Software, 2006
CountryUnited States
CityAustin, TX
Period3/19/063/21/06

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