The authors report on a complementary III-V heterostructure FET (HFET) technology that makes use of high AlAs mole fraction (Al,Ga)As barrier layers to reduce the gate leakage currents of n- and p-channel heterostructure FETs. The subthreshold currents and drain-to-gate leakage currents of p-HFETs are also substantially reduced as a result of the high AlAs mole fraction (Al,Ga)As barrier layer. A 1024 × 1 bit complementary HFET SRAM with access times as low as 4.6 ns and power dissipation of 34.8 mW has also been demonstrated using this technology.
|Original language||English (US)|
|Number of pages||4|
|Journal||Technical Digest - International Electron Devices Meeting|
|State||Published - Dec 1 1990|
|Event||1990 International Electron Devices Meeting - San Francisco, CA, USA|
Duration: Dec 9 1990 → Dec 12 1990