Unlike conventional electronic circuits, where transistors are placed in a single plane, three-dimensional (3D) integrated circuits utilize multiple tiers of active devices, placed one above another. Recent advances in processing technologies have brought these technologies into the realm of achievable reality, and today, several academic, corporate and government labs run fabrication processes for building 3D integrated circuits. The move to the third dimension immediately provides increased packing densities per unit footprint, and provides a path for maintaining Moore's law rates of growth at the system level, even as questions are being raised about the sustainability of device-level scaling. 3D circuits offer numerous other advantages as well, including the potential for reduced interconnect lengths, and the ability to easily integrate heterogeneous technologies on multiple tiers into a single package.This new paradigm brings forth a number of novel and interesting challenges, and raises the necessity for novel design and CAD techniques. A direct translation of a 2D design to 3D can lead to a suboptimal implementation that does not fully exploit the power of 3D, and 3D-specific approaches are essential. At the most fundamental level, 3D circuit design is a physical design problem; therefore, new methods for floorplanning, placement and routing must be developed within this paradigm. These techniques must work within the additional degrees of freedom as well as the new constraints imposed by this technology, such as restrictions on interlayer vias, as well as circuit limitations due to increased packing densities, particularly those related to the challenges of heat removal and power delivery.