Congestion-aware topology optimization of structured power/ground networks

Jaskirat Singh, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

29 Scopus citations


This paper presents an efficient method for optimizing the design of power/ground (P/G) networks by using locally regular, globally irregular grids. The procedure divides the power grid chip area into rectangular subgrids or tiles. Treating the entire power grid to be composed of many tiles connected to each other enables the use of a hierarchical circuit analysis approach to identify the tiles containing the nodes having the greatest drops. Starting from an initial configuration with an equal number of wires in each of the rectangular tiles, wires are added in the tiles using an iterative sensitivity based optimizer. A novel and efficient table lookup scheme is employed to provide gradient information to the optimizer. Incorporating a congestion penalty term in the cost function ensures that regularity in the grid structure does not aggravate congestion. Experimental results on test circuits of practical chip sizes show that the proposed P/G network topology, after optimization, saves 12%-23% of the chip-wiring area over other commonly used topologies.

Original languageEnglish (US)
Pages (from-to)683-695
Number of pages13
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number5
StatePublished - May 1 2005


  • Congestion-aware
  • Ground
  • Nonuniform grid
  • Power
  • Topology

Fingerprint Dive into the research topics of 'Congestion-aware topology optimization of structured power/ground networks'. Together they form a unique fingerprint.

Cite this