Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec

Lijun Gao, Keshnb K. Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

The issue of VLSI design of low latency/low power finite field multipliers is addressed and methods from logic structure, circuit design and physical mapping aspects are presented. With proposed architecture and physical mapping, an irregular balanced-tree parallel multiplier con be implemented as easy as a regular multiplier. The custom VLSI implementations of these multipliers over GF(2/sup m/) show that the irregular multiplier has 53% smaller delay and 58% less power consumption than a regular multiplier.

Original languageEnglish (US)
Title of host publicationISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Pages574-577
Number of pages4
DOIs
StatePublished - Dec 1 2001
Event2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001 - Sydney, NSW, Australia
Duration: May 6 2001May 9 2001

Publication series

NameISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings
Volume4

Other

Other2001 IEEE International Symposium on Circuits and Systems, ISCAS 2001
CountryAustralia
CitySydney, NSW
Period5/6/015/9/01

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