Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations

Jun Ma, Keshab K Parhi, Ed F. Deprettere

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

CORDIC based cascade orthogonal IIR digital filters have sharp transition band and exhibit low sensitivity in both pass band and stop band which are suitable for VLSI implementations. However, the achievable sample rate of these filters is limited due to the presence of feedback loops. To overcome the speed limitation and achieve high-speed/low-power implementations, a novel algorithm transformation technique is proposed based on retiming and orthogonal matrix decomposition techniques which can increase the maximum filter sample rate to O(1) level which is independent of the filter order. The proposed parallel and pipelined architectures consist of only Givens rotations which can be mapped onto CORDIC arithmetic based processors.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Symposium on Circuits and Systems
PublisherIEEE
Volume3
ISBN (Print)0780354710
StatePublished - Jan 1 1999
EventProceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99 - Orlando, FL, USA
Duration: May 30 1999Jun 2 1999

Other

OtherProceedings of the 1999 IEEE International Symposium on Circuits and Systems, ISCAS '99
CityOrlando, FL, USA
Period5/30/996/2/99

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