Design and implementation of LDPC codes for DVB-S2

Manoj K. Yadav, Keshab K Parhi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we present the design and FPGA implementation of 11 LDPC codes with code rates 1/4, 1/3, 2/5, 1/2, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9 and 9/10 for normal frame length of 64800 bits as used in DVB-S2. Out of these 11 codes, 7 are regular and 4 are irregular. All of them have been synthesized into Xilinx Virtex-II XC2V8000 FPGA.

Original languageEnglish (US)
Title of host publicationConference Record of The Thirty-Ninth Asilomar Conference on Signals, Systems and Computers
Pages723-728
Number of pages6
StatePublished - Dec 1 2005
Event39th Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, United States
Duration: Oct 28 2005Nov 1 2005

Publication series

NameConference Record - Asilomar Conference on Signals, Systems and Computers
Volume2005
ISSN (Print)1058-6393

Other

Other39th Asilomar Conference on Signals, Systems and Computers
CountryUnited States
CityPacific Grove, CA
Period10/28/0511/1/05

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