Abstract
Digit-serial architectures obtained using traditional unfolding techniques cannot be pipelined beyond a certain level because of the presence of feedback loops. In this paper, a novel design methodology is presented which permits bit-level pipelining of the digit-serial architectures. This enables bit-level pipelining of digit-serial architectures thereby achieving sample speeds close to corresponding bit-parallel multipliers with significantly lower area. This increased sample speed can be traded with reduction in power supply voltage resulting in significant reduction in power consumption. The results show that for transformed multipliers with smaller digit-sizes (≤4), the singly-redundant multiplier consumes the least power and for larger digit-sizes, the type-I multiplier consumes the least power. It is also found that the optimum digit-size for least power consumption in type-I and type-III multipliers is approximately √2W, where W represents the word-length. The proposed digit-serial multipliers consume on an average 20% lower power than the traditional digit-serial architectures for the non-pipelined case, and about 5-15 times lower power for the bit-level pipelined case. Also, modified Booth recoding is applied to transformed multipliers and it is found that the recoded multipliers consume about 22% lower power than the transformed multipliers without recoding.
Original language | English (US) |
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Title of host publication | Proceedings - IEEE International Conference on Computer Design |
Subtitle of host publication | VLSI in Computers and Processors |
Editors | Anon |
Publisher | IEEE |
Pages | 186-195 |
Number of pages | 10 |
State | Published - Dec 1 1997 |
Event | Proceedings of the 1997 International Conference on Computer Design - Austin, TX, USA Duration: Oct 12 1997 → Oct 15 1997 |
Other
Other | Proceedings of the 1997 International Conference on Computer Design |
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City | Austin, TX, USA |
Period | 10/12/97 → 10/15/97 |