This paper presents novel approaches for pipelining of parallel nested multiplexer loops and decision feedback equalizers (DFEs) based on look-ahead techniques. Look-ahead techniques can be applied to pipeline a nested multiplexer loop in many possible ways. It is shown that not all the look-ahead approaches necessarily result in improved performance. A novel look-ahead approach is identified, which can guarantee improvement in performance either in the form of pipelining or parallelism. The proposed technique is demonstrated and applied to design multiplexer-loop-based DFEs with throughput in the range of 3.125-10 Gb/s.
|Original language||English (US)|
|Number of pages||5|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Apr 1 2005|
- Decision feedback equalizers (DFEs)
- Multiplexer loop