Design of multigigabit multiplexer-loop-based decision feedback equalizers

Keshab K. Parhi

doi:10.1109/TVLSI.2004.842935

Design of multigigabit multiplexer-loop-based decision feedback equalizers

Keshab K. Parhi

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

48 Scopus citations

Abstract

This paper presents novel approaches for pipelining of parallel nested multiplexer loops and decision feedback equalizers (DFEs) based on look-ahead techniques. Look-ahead techniques can be applied to pipeline a nested multiplexer loop in many possible ways. It is shown that not all the look-ahead approaches necessarily result in improved performance. A novel look-ahead approach is identified, which can guarantee improvement in performance either in the form of pipelining or parallelism. The proposed technique is demonstrated and applied to design multiplexer-loop-based DFEs with throughput in the range of 3.125-10 Gb/s.

Original language	English (US)
Pages (from-to)	489-493
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	13
Issue number	4
DOIs	https://doi.org/10.1109/TVLSI.2004.842935
State	Published - Apr 2005

Keywords

Decision feedback equalizers (DFEs)
Look-ahead
Multiplexer loop
Pipelining

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Design of multigigabit multiplexer-loop-based decision feedback equalizers

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