Like decision feedback equalizers (DFEs), Tomlinson-Harashima precoders (TH precoders) contain nonlinear feedback loops, which limit their use for high-speed applications. Unlike in DFEs, where the output levels of the nonlinear devices are finite, in TH precoders the output levels of the modulo devices are either infinite or finite but very large. Thus, it is difficult to apply look-ahead and pre-computation techniques to speed up TH precoders, which were successfully applied to design parallel and pipelined infinite impulse response (IIR) filters and DFEs in the past. However, a TH precoder can be viewed as an IIR filter with an input equal to the sum of the original input to the TH precoder and a finite-level compensation signal. Based on this point of view, a novel parallel architecture is proposed to speed up TH precoders. This architecture can be used in many high-speed applications, such as 10-Gb Ethernet over copper.
|Original language||English (US)|
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|State||Published - May 2008|
Bibliographical noteFunding Information:
Manuscript received May 30, 2007; revised September 23, 2007. This work was supported in part by the National Science Foundation under the SBIR Grant DMI-0441632. This work was carried out by the authors for the Leanics Corporation, Maple Grove, MN. Part of this paper appeared in the patent application “Parallel Tomlinson–Harashima Precoders.” This paper was recommended by Associate Editor T. Stouraitis.
Copyright 2008 Elsevier B.V., All rights reserved.
- High-speed Ethernet transceiver
- Parallel processing
- Tomlinson-Harashima precoder