Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators

Saurabh Chaubey; Meghna Madhusudan; Ramesh Harjani

doi:10.1109/MWSCAS.2019.8885068

Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators

Saurabh Chaubey, Meghna Madhusudan, Ramesh Harjani

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

We present two technology portable design techniques to achieve zero steady-state output voltage ripple in digital LDOs. Traditional digital LDOs have an inherent output voltage ripple due to the limit cycle oscillations at a frequency of F_clock/(2×Mode). We use a 4-bit digital LDO as the test vehicle to investigate these two new techniques. The power-switch bank consists of PMOS HVT (high threshold) devices. The first method uses body biasing of the switches via an auxiliary analog loop to minimize the ripple voltage. Effectively, the analog loop enables the power switches to carry the extra ripple current and has little impact on the efficiency. In the second method, zero steady-state ripple is achieved by modulating the gate-driver voltage-swings at the power-switch gate. In both the techniques, when the digital LDO is in steady state, the analog loop only carries the ripple current magnitude. Control from the analog and digital loops are ping-ponged based on load transients. The LDO design handles inputs from 0.5-1.5V and supports a 0.4-1.2V output voltage for a load range of 0.1-to-20mA (200X). The LDO achieves 99.4% current efficiency and near-zero output voltage ripple. The total area of chip is 0.08mm² in TSMC 65nm CMOS GP.

Original language	English (US)
Title of host publication	2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, MWSCAS 2019
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	1041-1044
Number of pages	4
ISBN (Electronic)	9781728127880
DOIs	https://doi.org/10.1109/MWSCAS.2019.8885068
State	Published - Aug 2019
Event	62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019 - Dallas, United States Duration: Aug 4 2019 → Aug 7 2019

Publication series

Name	Midwest Symposium on Circuits and Systems
Volume	2019-August
ISSN (Print)	1548-3746

Conference

Conference	62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019
Country/Territory	United States
City	Dallas
Period	8/4/19 → 8/7/19

Bibliographical note

Funding Information:
This work was supported by SRC task ID 2712.008. REFERENCES

Publisher Copyright:
© 2019 IEEE.

Access

10.1109/MWSCAS.2019.8885068

OpenUrl availability

Full text

Cite this

Chaubey, S., Madhusudan, M., & Harjani, R. (2019). Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators. In 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, MWSCAS 2019 (pp. 1041-1044). Article 8885068 (Midwest Symposium on Circuits and Systems; Vol. 2019-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/MWSCAS.2019.8885068

Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators. / Chaubey, Saurabh; Madhusudan, Meghna; Harjani, Ramesh.
2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, MWSCAS 2019. Institute of Electrical and Electronics Engineers Inc., 2019. p. 1041-1044 8885068 (Midwest Symposium on Circuits and Systems; Vol. 2019-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Chaubey, S, Madhusudan, M & Harjani, R 2019, Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators. in 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, MWSCAS 2019., 8885068, Midwest Symposium on Circuits and Systems, vol. 2019-August, Institute of Electrical and Electronics Engineers Inc., pp. 1041-1044, 62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019, Dallas, United States, 8/4/19. https://doi.org/10.1109/MWSCAS.2019.8885068

Chaubey S, Madhusudan M, Harjani R. Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators. In 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, MWSCAS 2019. Institute of Electrical and Electronics Engineers Inc. 2019. p. 1041-1044. 8885068. (Midwest Symposium on Circuits and Systems). doi: 10.1109/MWSCAS.2019.8885068

@inproceedings{ffc4b43444cb4eb1b4df1b8297c40755,

title = "Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators",

abstract = "We present two technology portable design techniques to achieve zero steady-state output voltage ripple in digital LDOs. Traditional digital LDOs have an inherent output voltage ripple due to the limit cycle oscillations at a frequency of Fclock/(2×Mode). We use a 4-bit digital LDO as the test vehicle to investigate these two new techniques. The power-switch bank consists of PMOS HVT (high threshold) devices. The first method uses body biasing of the switches via an auxiliary analog loop to minimize the ripple voltage. Effectively, the analog loop enables the power switches to carry the extra ripple current and has little impact on the efficiency. In the second method, zero steady-state ripple is achieved by modulating the gate-driver voltage-swings at the power-switch gate. In both the techniques, when the digital LDO is in steady state, the analog loop only carries the ripple current magnitude. Control from the analog and digital loops are ping-ponged based on load transients. The LDO design handles inputs from 0.5-1.5V and supports a 0.4-1.2V output voltage for a load range of 0.1-to-20mA (200X). The LDO achieves 99.4% current efficiency and near-zero output voltage ripple. The total area of chip is 0.08mm2 in TSMC 65nm CMOS GP.",

author = "Saurabh Chaubey and Meghna Madhusudan and Ramesh Harjani",

note = "Funding Information: This work was supported by SRC task ID 2712.008. REFERENCES Publisher Copyright: {\textcopyright} 2019 IEEE.; 62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019 ; Conference date: 04-08-2019 Through 07-08-2019",

year = "2019",

month = aug,

doi = "10.1109/MWSCAS.2019.8885068",

language = "English (US)",

series = "Midwest Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "1041--1044",

booktitle = "2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, MWSCAS 2019",

}

TY - GEN

T1 - Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators

AU - Chaubey, Saurabh

AU - Madhusudan, Meghna

AU - Harjani, Ramesh

PY - 2019/8

Y1 - 2019/8

N2 - We present two technology portable design techniques to achieve zero steady-state output voltage ripple in digital LDOs. Traditional digital LDOs have an inherent output voltage ripple due to the limit cycle oscillations at a frequency of Fclock/(2×Mode). We use a 4-bit digital LDO as the test vehicle to investigate these two new techniques. The power-switch bank consists of PMOS HVT (high threshold) devices. The first method uses body biasing of the switches via an auxiliary analog loop to minimize the ripple voltage. Effectively, the analog loop enables the power switches to carry the extra ripple current and has little impact on the efficiency. In the second method, zero steady-state ripple is achieved by modulating the gate-driver voltage-swings at the power-switch gate. In both the techniques, when the digital LDO is in steady state, the analog loop only carries the ripple current magnitude. Control from the analog and digital loops are ping-ponged based on load transients. The LDO design handles inputs from 0.5-1.5V and supports a 0.4-1.2V output voltage for a load range of 0.1-to-20mA (200X). The LDO achieves 99.4% current efficiency and near-zero output voltage ripple. The total area of chip is 0.08mm2 in TSMC 65nm CMOS GP.

AB - We present two technology portable design techniques to achieve zero steady-state output voltage ripple in digital LDOs. Traditional digital LDOs have an inherent output voltage ripple due to the limit cycle oscillations at a frequency of Fclock/(2×Mode). We use a 4-bit digital LDO as the test vehicle to investigate these two new techniques. The power-switch bank consists of PMOS HVT (high threshold) devices. The first method uses body biasing of the switches via an auxiliary analog loop to minimize the ripple voltage. Effectively, the analog loop enables the power switches to carry the extra ripple current and has little impact on the efficiency. In the second method, zero steady-state ripple is achieved by modulating the gate-driver voltage-swings at the power-switch gate. In both the techniques, when the digital LDO is in steady state, the analog loop only carries the ripple current magnitude. Control from the analog and digital loops are ping-ponged based on load transients. The LDO design handles inputs from 0.5-1.5V and supports a 0.4-1.2V output voltage for a load range of 0.1-to-20mA (200X). The LDO achieves 99.4% current efficiency and near-zero output voltage ripple. The total area of chip is 0.08mm2 in TSMC 65nm CMOS GP.

UR - http://www.scopus.com/inward/record.url?scp=85075000249&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85075000249&partnerID=8YFLogxK

U2 - 10.1109/MWSCAS.2019.8885068

DO - 10.1109/MWSCAS.2019.8885068

M3 - Conference contribution

AN - SCOPUS:85075000249

T3 - Midwest Symposium on Circuits and Systems

SP - 1041

EP - 1044

BT - 2019 IEEE 62nd International Midwest Symposium on Circuits and Systems, MWSCAS 2019

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 62nd IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2019

Y2 - 4 August 2019 through 7 August 2019

ER -

Design Techniques for Zero Steady-State Output Ripple in Digital Low Dropout Regulators

Abstract

Publication series

Conference

Bibliographical note

Access

OpenUrl availability

Other files and links

Fingerprint

Cite this