DFT for digital detection of analog parametric faults in SC filters

Bapiraju Vinnakota, Ramesh Harjani

Research output: Contribution to journalArticlepeer-review

16 Scopus citations

Abstract

Parametric faults are a significant cause of incorrect operation in analog circuits. Many design for test techniques for analog circuits are ineffective at detecting multiple parametric faults because either their accuracy is poor, or the circuit is not tested in the configuration in which it is used. We present a design for test (DFT) scheme that offers the accuracy needed to test high-quality circuits. The DFT scheme is based on a circuit that digitally measures the ratio of a pair of capacitors. The circuit is used to characterize the transfer function of a switched capacitor circuit, which is usually determined by capacitor ratios. In our DFT scheme, capacitor ratios can be measured to within 0.01% accuracy and filter parameters can be shown to be satisfied to within 0.1% accuracy. With this characterization process, a filter can be directly shown to satisfy all specifications that depend on capacitor ratios. We believe the accuracy of our approach is at least an order of magnitude greater than that offered by any other DFT scheme reported in the literature.

Original languageEnglish (US)
Pages (from-to)789-798
Number of pages10
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Volume19
Issue number7
DOIs
StatePublished - Jul 2000

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