The authors present a systematic unfolding transformation technique to transform bit-serial architectures into equivalent digit-serial ones. The novel feature of the technique is the generation of functionally correct control circuits in the digit-serial architectures. Bit-serial systems process one bit of a word or sample in a clock cycle. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and may require too much hardware. The desired sample rate can be achieved using the digit-serial approach, where multiple bits of a sample are processed in a single clock cycle. The number of bits processed in one clock cycle in the digit-serial systems is the digit size; the digit size can be any arbitrary integer. A digit-serial implementation of two's complement adders and multipliers is presented. Unfolding of multiple-rate operations (such as interpolators and decimators) is also presented.