Digit-serial DSP architectures

Keshab K. Parhi, Ching Yi Wang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations


The authors present a systematic unfolding transformation technique to transform bit-serial architectures into equivalent digit-serial ones. The novel feature of the technique is the generation of functionally correct control circuits in the digit-serial architectures. Bit-serial systems process one bit of a word or sample in a clock cycle. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and may require too much hardware. The desired sample rate can be achieved using the digit-serial approach, where multiple bits of a sample are processed in a single clock cycle. The number of bits processed in one clock cycle in the digit-serial systems is the digit size; the digit size can be any arbitrary integer. A digit-serial implementation of two's complement adders and multipliers is presented. Unfolding of multiple-rate operations (such as interpolators and decimators) is also presented.

Original languageEnglish (US)
Title of host publicationProc 90 Int Conf Appl Specif Array Process
PublisherPubl by IEEE
Number of pages11
ISBN (Print)0818690895
StatePublished - Jan 1 1991
EventProceedings of the 1990 International Conference on Application Specific Array Processors - Princeton, NJ, USA
Duration: Sep 5 1990Sep 7 1990

Publication series

NameProc 90 Int Conf Appl Specif Array Process


OtherProceedings of the 1990 International Conference on Application Specific Array Processors
CityPrinceton, NJ, USA


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