Digit-serial fixed coefficient complex number multiplier-accumulator on FPGAs

Trini Sansaloni, Javier Valls, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


In this paper we consider the design of a digit-serial multiplier for the implementation of a complex numbers multiplier-accumulator (CMAC) on FPGAs. In this case, fixed coefficient multipliers and pipelined at LUT-level structures have been considered. Partial products generator based in look-up tables and Multibit Booth recoding are used to reduce the area and increase the performance of the circuit. The efficient mapping of the 5 bits Booth recoding to generate the partial products is presented as the optimum multibit recoding when Xilinx FPGA devices are used.

Original languageEnglish (US)
Pages (from-to)236-240
Number of pages5
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
StatePublished - Jan 1 2000


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