Abstract
In this paper we consider the design of a digit-serial multiplier for the implementation of a complex numbers multiplier-accumulator (CMAC) on FPGAs. In this case, fixed coefficient multipliers and pipelined at LUT-level structures have been considered. Partial products generator based in look-up tables and Multibit Booth recoding are used to reduce the area and increase the performance of the circuit. The efficient mapping of the 5 bits Booth recoding to generate the partial products is presented as the optimum multibit recoding when Xilinx FPGA devices are used.
Original language | English (US) |
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Pages (from-to) | 236-240 |
Number of pages | 5 |
Journal | Proceedings of the Annual IEEE International ASIC Conference and Exhibit |
DOIs | |
State | Published - 2000 |