A novel connection between digit-serial computing and skew-tolerant domino circuit design is developed and applied to the design of unsigned and signed multipliers. In our design methodology, a multiplier having a digit size of N bits is naturally and efficiently mapped into a skew-tolerant domino implementation using N overlapping clock phases. In order to demonstrate the performance advantage of our approach, we compare two types of multiplier implementations, one constructed using traditional domino circuits and the other using the skew-tolerant domino technique. The simulation results show that a particular digit-serial multiplier constructed with skew-tolerant domino circuits is up to 41% faster than the corresponding design with traditional domino circuits.
|Original language||English (US)|
|Number of pages||5|
|Journal||Proceedings of the Annual IEEE International ASIC Conference and Exhibit|
|State||Published - Jan 1 2001|