TY - JOUR
T1 - Distributed on-chip switched-capacitor DC-DC converters supporting DVFS in multicore systems
AU - Zhou, Pingqiang
AU - Paul, Ayan
AU - Kim, Chris H.
AU - Sapatnekar, Sachin S.
PY - 2014/9
Y1 - 2014/9
N2 - Dynamic voltage and frequency scaling (DVFS) is a powerful technique to reduce power consumption in a chip multiprocessor. To support DVFS in the multicore power delivery network, we integrate on-chip switched-capacitor (SC) dc-dc converters that can work with multiple conversion ratios to provide varying levels of Vdd supplies. We study the application of such SC converters in multicore chips by simulation. Our results show that distributed SC converters can significantly reduce the voltage droop seen by the local core loads by providing better localized power regulation. Considering the fact that the current distribution in a multicore chip is unbalanced, we further develop computer-aided design techniques to automate the design (size) and distribution (number and location) of these SC converters, using the efficiency of the whole power delivery system as the optimization metric. This is a major concern, but has not been addressed at the system level in prior research. We develop models for the power loss of such a system as a function of size and distribution of the SC converters, then propose an approach to optimize the SC converters to maximize the efficiency of the system, while considering all the possible conversion ratios an SC converter can work with. We verify the accuracy of our models for the power loss in the power delivery system, and demonstrate the efficiency of our techniques to optimize the SC converters on both homogenous and heterogenous multicore chips.
AB - Dynamic voltage and frequency scaling (DVFS) is a powerful technique to reduce power consumption in a chip multiprocessor. To support DVFS in the multicore power delivery network, we integrate on-chip switched-capacitor (SC) dc-dc converters that can work with multiple conversion ratios to provide varying levels of Vdd supplies. We study the application of such SC converters in multicore chips by simulation. Our results show that distributed SC converters can significantly reduce the voltage droop seen by the local core loads by providing better localized power regulation. Considering the fact that the current distribution in a multicore chip is unbalanced, we further develop computer-aided design techniques to automate the design (size) and distribution (number and location) of these SC converters, using the efficiency of the whole power delivery system as the optimization metric. This is a major concern, but has not been addressed at the system level in prior research. We develop models for the power loss of such a system as a function of size and distribution of the SC converters, then propose an approach to optimize the SC converters to maximize the efficiency of the system, while considering all the possible conversion ratios an SC converter can work with. We verify the accuracy of our models for the power loss in the power delivery system, and demonstrate the efficiency of our techniques to optimize the SC converters on both homogenous and heterogenous multicore chips.
KW - Chip multiprocessor (CMP)
KW - Dynamic voltage and frequency scaling (DVFS)
KW - Efficiency
KW - MILP
KW - On-chip switched-capacitor dc-dc converter
UR - http://www.scopus.com/inward/record.url?scp=84906948663&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84906948663&partnerID=8YFLogxK
U2 - 10.1109/TVLSI.2013.2280139
DO - 10.1109/TVLSI.2013.2280139
M3 - Article
AN - SCOPUS:84906948663
SN - 1063-8210
VL - 22
SP - 1954
EP - 1967
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IS - 9
M1 - 6609141
ER -