Dynamic Vt SRAM: A leakage tolerant cache memory for low voltage microprocessors

Chris H. Kim; Kaushik Roy

Dynamic Vt SRAM: A leakage tolerant cache memory for low voltage microprocessors

Chris H. Kim, Kaushik Roy

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

67 Scopus citations

Abstract

This paper presents a Dynamic Vt SRAM (DTSRAM) architecture to reduce the subthreshold leakage in cache memories. The Vt of each cache line is controlled separately by means of body biasing. In order to minimize the energy and delay overhead, a cache line is switched to high Vt only when it is not likely to be accessed anymore. Simulation results from SimpleScalar framework show that even after considering the energy overhead, the DTSRAM can save 72% of the cache leakage with a performance loss less than 1%. Layout of the DTSRAM shows that the area penalty is minimal.

Original language	English (US)
Title of host publication	Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers
Pages	251-254
Number of pages	4
State	Published - Dec 1 2002
Event	Proceedings of the 2002 International Symposium on Low Power Electronics and Design - Monterey, CA, United States Duration: Aug 12 2002 → Aug 14 2002

Other

Other	Proceedings of the 2002 International Symposium on Low Power Electronics and Design
Country/Territory	United States
City	Monterey, CA
Period	8/12/02 → 8/14/02

OpenUrl availability

Full text

Cite this

@inproceedings{8d64713fa7d84acead277ac23fa4ffb9,

title = "Dynamic Vt SRAM: A leakage tolerant cache memory for low voltage microprocessors",

abstract = "This paper presents a Dynamic Vt SRAM (DTSRAM) architecture to reduce the subthreshold leakage in cache memories. The Vt of each cache line is controlled separately by means of body biasing. In order to minimize the energy and delay overhead, a cache line is switched to high Vt only when it is not likely to be accessed anymore. Simulation results from SimpleScalar framework show that even after considering the energy overhead, the DTSRAM can save 72% of the cache leakage with a performance loss less than 1%. Layout of the DTSRAM shows that the area penalty is minimal.",

author = "Kim, {Chris H.} and Kaushik Roy",

year = "2002",

month = dec,

day = "1",

language = "English (US)",

pages = "251--254",

booktitle = "Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers",

note = "Proceedings of the 2002 International Symposium on Low Power Electronics and Design ; Conference date: 12-08-2002 Through 14-08-2002",

}

TY - GEN

T1 - Dynamic Vt SRAM

T2 - Proceedings of the 2002 International Symposium on Low Power Electronics and Design

AU - Kim, Chris H.

AU - Roy, Kaushik

PY - 2002/12/1

Y1 - 2002/12/1

N2 - This paper presents a Dynamic Vt SRAM (DTSRAM) architecture to reduce the subthreshold leakage in cache memories. The Vt of each cache line is controlled separately by means of body biasing. In order to minimize the energy and delay overhead, a cache line is switched to high Vt only when it is not likely to be accessed anymore. Simulation results from SimpleScalar framework show that even after considering the energy overhead, the DTSRAM can save 72% of the cache leakage with a performance loss less than 1%. Layout of the DTSRAM shows that the area penalty is minimal.

AB - This paper presents a Dynamic Vt SRAM (DTSRAM) architecture to reduce the subthreshold leakage in cache memories. The Vt of each cache line is controlled separately by means of body biasing. In order to minimize the energy and delay overhead, a cache line is switched to high Vt only when it is not likely to be accessed anymore. Simulation results from SimpleScalar framework show that even after considering the energy overhead, the DTSRAM can save 72% of the cache leakage with a performance loss less than 1%. Layout of the DTSRAM shows that the area penalty is minimal.

UR - http://www.scopus.com/inward/record.url?scp=0036949567&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0036949567&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:0036949567

SP - 251

EP - 254

BT - Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Y2 - 12 August 2002 through 14 August 2002

ER -

Dynamic Vt SRAM: A leakage tolerant cache memory for low voltage microprocessors

Abstract

Other

OpenUrl availability

Other files and links

Fingerprint

Cite this