The morphology, structure, and transport properties of pentacene thin film transistors (TFTs) are reported showing the influence of the gate dielectric surface roughness. Upon roughening of the amorphous SiO 2 gate dielectric prior to pentacene deposition, dramatic reductions in pentacene grain size and crystallinity were observed. The TFT performance of pentacene films deposited on roughened substrates showed reduced free carrier mobility, larger transport activation energies, and larger trap distribution widths. Spin coating roughened dielectrics with polystyrene produced surfaces with 2 Å root-mean-square (rms) roughness. The pentacene films deposited on these coated surfaces had grain sizes, crystallinities, mobilities, and trap distributions that were comparable to the range of values observed for pentacene films deposited on thermally grown SiO 2 (roughness also ∼2 Å rms).