Abstract
In the built-in self-test (BIST) methodology, the two major problems which must be addressed are test generation and response analysis. An efficient, unified solution to the problem of test generation is presented. A design procedure that is computationally efficient and produces test generation circuitry with low hardware overhead is proposed. The effectiveness of this approach is demonstrated by detailed comparisons of its results with those that would be obtained by existing techniques.
| Original language | English (US) |
|---|---|
| Title of host publication | Proceedings - IEEE International Conference on Computer Design |
| Subtitle of host publication | VLSI in Computers and Processors |
| Editors | Anon |
| Publisher | Publ by IEEE |
| Pages | 576-579 |
| Number of pages | 4 |
| State | Published - Dec 1 1989 |
| Event | Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA Duration: Oct 2 1989 → Oct 4 1989 |
Other
| Other | Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors |
|---|---|
| City | Cambridge, MA, USA |
| Period | 10/2/89 → 10/4/89 |