Abstract
In this paper, we consider the problem of finding all-pairs input-to-output delays for combinational circuits. This method is of practical utility in several design situations and CAD algorithms, for example in [1,2]. An algorithm for solving this problem was proposed in [1]; however, this can be computationally expensive. We take advantage of some properties of large realistic circuits to present an algorithm that is two orders of magnitude faster than the method in [1] for large circuits. Experimental results on ISCAS benchmark circuits prove the efficacy of this approach.
| Original language | English (US) |
|---|---|
| Pages (from-to) | 520-523 |
| Number of pages | 4 |
| Journal | Proceedings - IEEE International Symposium on Circuits and Systems |
| Volume | 4 |
| State | Published - 1996 |
| Event | Proceedings of the 1996 IEEE International Symposium on Circuits and Systems, ISCAS. Part 1 (of 4) - Atlanta, GA, USA Duration: May 12 1996 → May 15 1996 |