TY - GEN
T1 - Efficient generation of all minimal inductive validity cores
AU - Ghassabani, Elaheh
AU - Whalen, Michael
AU - Gacek, Andrew
N1 - Publisher Copyright:
© 2017 FMCAD Inc.
Copyright:
Copyright 2018 Elsevier B.V., All rights reserved.
PY - 2017/11/8
Y1 - 2017/11/8
N2 - Symbolic model checkers can construct proofs of safety properties over complex models, but when a proof succeeds, the results do not generally provide much insight to the user. Recently, proof cores (alternately, for inductive model checkers, Inductive Validity Cores (IVCs)) were introduced to trace a property to a minimal set of model elements necessary for proof. Minimal IVCs facilitate several engineering tasks, including performing traceability and analyzing requirements completeness, that usually rely on the minimality of IVCs. However, existing algorithms for generating an IVC are either expensive or only able to find an approximately minimal IVC. Besides minimality, computing all minimal IVCs of a given property is an interesting problem that provides several useful analyses, including regression analysis for testing/proof, determination of the minimum (as opposed to minimal) number of model elements necessary for proof, the diversity examination of model elements leading to proof, and analyzing fault tolerance. This paper proposes an efficient method for finding all minimal IVCs of a given property proving its correctness and completeness. We benchmark our algorithm against existing IVC-generating algorithms and show, in many cases, the cost of finding all minimal IVCs by our technique is similar to finding a single minimal IVC using existing algorithms.
AB - Symbolic model checkers can construct proofs of safety properties over complex models, but when a proof succeeds, the results do not generally provide much insight to the user. Recently, proof cores (alternately, for inductive model checkers, Inductive Validity Cores (IVCs)) were introduced to trace a property to a minimal set of model elements necessary for proof. Minimal IVCs facilitate several engineering tasks, including performing traceability and analyzing requirements completeness, that usually rely on the minimality of IVCs. However, existing algorithms for generating an IVC are either expensive or only able to find an approximately minimal IVC. Besides minimality, computing all minimal IVCs of a given property is an interesting problem that provides several useful analyses, including regression analysis for testing/proof, determination of the minimum (as opposed to minimal) number of model elements necessary for proof, the diversity examination of model elements leading to proof, and analyzing fault tolerance. This paper proposes an efficient method for finding all minimal IVCs of a given property proving its correctness and completeness. We benchmark our algorithm against existing IVC-generating algorithms and show, in many cases, the cost of finding all minimal IVCs by our technique is similar to finding a single minimal IVC using existing algorithms.
KW - Inductive proofs
KW - Inductive Validity Cores
KW - SMT-based model checking
KW - UNSAT-core generation
UR - http://www.scopus.com/inward/record.url?scp=85041433109&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85041433109&partnerID=8YFLogxK
U2 - 10.23919/FMCAD.2017.8102238
DO - 10.23919/FMCAD.2017.8102238
M3 - Conference contribution
AN - SCOPUS:85041433109
T3 - Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017
SP - 31
EP - 38
BT - Proceedings of the 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017
A2 - Weissenbacher, Georg
A2 - Stewart, Daryl
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 17th Conference on Formal Methods in Computer-Aided Design, FMCAD 2017
Y2 - 2 October 2017 through 6 October 2017
ER -