TY - JOUR
T1 - Efficient minarea retiming of large level-clocked circuits
AU - Maheshwari, Naresh
AU - Sapatnekar, Sachin S.
PY - 1998/12/1
Y1 - 1998/12/1
N2 - Delay-constrained area optimization is an important step in synthesis of VLSI circuits. Minimum area (minarea) retiming is a powerful technique to solve this problem. The minarea retiming problem has been formulated as a linear program; in this work we present techniques for reducing the size of this linear program and efficient techniques for generating it. This results in an efficient minarea retiming method for large level-clocked circuits (with tens of thousands of gates).
AB - Delay-constrained area optimization is an important step in synthesis of VLSI circuits. Minimum area (minarea) retiming is a powerful technique to solve this problem. The minarea retiming problem has been formulated as a linear program; in this work we present techniques for reducing the size of this linear program and efficient techniques for generating it. This results in an efficient minarea retiming method for large level-clocked circuits (with tens of thousands of gates).
UR - http://www.scopus.com/inward/record.url?scp=84893741528&partnerID=8YFLogxK
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U2 - 10.1109/DATE.1998.655956
DO - 10.1109/DATE.1998.655956
M3 - Conference article
AN - SCOPUS:84893741528
SN - 1530-1591
SP - 840
EP - 845
JO - Proceedings -Design, Automation and Test in Europe, DATE
JF - Proceedings -Design, Automation and Test in Europe, DATE
M1 - 655956
T2 - Design, Automation and Test in Europe, DATE 1998
Y2 - 23 February 1998 through 26 February 1998
ER -