Delay-constrained area optimization is an important step in synthesis of VLSI circuits. Minimum area (minarea) retiming is a powerful technique to solve this problem. The minarea retiming problem has been formulated as a linear program; in this work we present techniques for reducing the size of this linear program and efficient techniques for generating it. This results in an efficient minarea retiming method for large level-clocked circuits (with tens of thousands of gates).
|Original language||English (US)|
|Number of pages||6|
|Journal||Proceedings -Design, Automation and Test in Europe, DATE|
|State||Published - Dec 1 1998|
|Event||Design, Automation and Test in Europe, DATE 1998 - Paris, France|
Duration: Feb 23 1998 → Feb 26 1998