Energy/delay tradeoffs in all-spin logic circuits

All-spin logic (ASL) is a spin-based candidate for implementing logic in the next generation designs. The energy and the delay of ASL circuits are both inherently related to the geometric parameters of ASL gates, and the careful selection of the dimensions for ASL gates is required to achieve optimal performance. In this paper, a tradeoff relation between the energy and the delay is explored to optimally size the magnets and channels in an ASL gate to provide an optimal balance under various delay and energy demands. Results on optimizing interconnects and benchmark circuits are presented.