@inproceedings{6cd475411d5a48db84914b14faf46323,
title = "Estimation and optimization of reliability of noisy digital circuits",
abstract = "With continued scaling, reliability is emerging as a critical challenge for the designers of digital circuits. The challenge stems in part from the lack of computationally efficient techniques for analyzing and optimizing circuits for reliability. To address this problem, we propose an exact analysis method based on circuit transformations. Also, we propose a hybrid method that combines exact analysis with probabilistic measures to estimate reliability. We use such measures in a rewiring-based optimization framework to optimize reliability. Our hybrid approach offers a speedup of 56X when compared to a pure Monte Carlo simulation-based approach with only a 3.5% loss in accuracy. Our optimization framework improves reliability by about 10% accompanied by a 6.9% reduction in circuit area.",
keywords = "And Fault-Tolerance, Automatic Synthesis, Optimization, Reliability, Testing",
author = "Satish Sivaswamy and Kia Bazargan and Marc Riedel",
year = "2009",
doi = "10.1109/ISQED.2009.4810296",
language = "English (US)",
isbn = "9781424429530",
series = "Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009",
pages = "213--219",
booktitle = "Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009",
note = "10th International Symposium on Quality Electronic Design, ISQED 2009 ; Conference date: 16-03-2009 Through 18-03-2009",
}