Estimation and optimization of reliability of noisy digital circuits

Satish Sivaswamy, Kia Bazargan, Marc Riedel

Research output: Chapter in Book/Report/Conference proceedingConference contribution

21 Scopus citations

Abstract

With continued scaling, reliability is emerging as a critical challenge for the designers of digital circuits. The challenge stems in part from the lack of computationally efficient techniques for analyzing and optimizing circuits for reliability. To address this problem, we propose an exact analysis method based on circuit transformations. Also, we propose a hybrid method that combines exact analysis with probabilistic measures to estimate reliability. We use such measures in a rewiring-based optimization framework to optimize reliability. Our hybrid approach offers a speedup of 56X when compared to a pure Monte Carlo simulation-based approach with only a 3.5% loss in accuracy. Our optimization framework improves reliability by about 10% accompanied by a 6.9% reduction in circuit area.

Original languageEnglish (US)
Title of host publicationProceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009
Pages213-219
Number of pages7
DOIs
StatePublished - 2009
Event10th International Symposium on Quality Electronic Design, ISQED 2009 - San Jose, CA, United States
Duration: Mar 16 2009Mar 18 2009

Publication series

NameProceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009

Other

Other10th International Symposium on Quality Electronic Design, ISQED 2009
Country/TerritoryUnited States
CitySan Jose, CA
Period3/16/093/18/09

Keywords

  • And Fault-Tolerance
  • Automatic Synthesis
  • Optimization
  • Reliability
  • Testing

Fingerprint

Dive into the research topics of 'Estimation and optimization of reliability of noisy digital circuits'. Together they form a unique fingerprint.

Cite this