@inproceedings{893217531cec4d9d8b32f3810ea96576,
title = "Exact lower bound for the number of switches in series to implement a combinational logic cell",
abstract = "This paper addresses the question of how many serial switches are necessary to implement a given logic function as a switch network. This issue is important because it affects directly the resistance that will be charging/discharging output loads, thus affecting cell and circuit performance. We derive exact lower bounds to easily evaluate the number of serial switches needed and demonstrate that Complementary Series/Parallel (CSP) and Pass Transistor Logic (PTL) topologies exceed the lower bounds for many practical examples. We also propose a design methodology that will produce cells with minimum number of transistors in series and evaluate the benefits obtained in circuit delay.",
author = "Schneider, {F. R.} and Ribas, {R. P.} and Sapatnekar, {S. S.} and Reis, {A. I.}",
year = "2005",
doi = "10.1109/ICCD.2005.51",
language = "English (US)",
isbn = "0769524516",
series = "Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors",
pages = "357--362",
booktitle = "Proceedings - 2005 IEEE International Conference on Computer Design",
note = "2005 IEEE International Conference on Computer Design: VLSI in Computers and Processors, ICCD 2005 ; Conference date: 02-10-2005 Through 05-10-2005",
}