Scheduling and retiming are important techniques used in the design of hardware and software implementations of digital signal processing algorithms. In this paper, techniques are developed for generating all scheduling and retiming solutions for a strongly connected data-flow graph, allowing a designer to explore the space of possible implementations. Formulations are developed for two scheduling problems. The first scheduling problem assumes a bit-parallel target architecture. The formulation for this problem is general because it considers retiming the data-flow graph as part of scheduling, and this formulation reduces to the retiming formulation as a special case. The second scheduling problem assumes a bit-serial target architecture. Based on these formulations, the conditions for a legal scheduling solution are derived, and a systematic technique is presented for exhaustively generating all legal scheduling solutions for a strongly connected data-flow graph. Since retiming is a special case of scheduling, this systematic technique can also be used for exhaustively generating all legal retiming solutions. A technique is also developed for exhaustively generating only those bit-parallel schedules which satisfy a given set of resource constraints. The techniques for exhaustively generating scheduling and retiming solutions are demonstrated for several filters. For example, we show that a simple filter such as the biquad has 224 possible retiming solutions for a latency of one time unit. We also show that a fifth-order wave digital elliptic filter has 4.7 million and 580 million scheduling solutions for iteration periods of 17 and 18, respectively.
|Original language||English (US)|
|Number of pages||18|
|Journal||IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing|
|State||Published - 1998|
Bibliographical noteFunding Information:
Manuscript received May 7, 1996; revised December 11, 1997. This work was supported by the Advanced Research Projects Agency and the Solid State Electronics Directorate, Wright-Patterson AFB, under Contract AF/F33615-93-C-1309. This paper was recommended by Associate Editor B. A. Shenoi. T. C. Denk was with Bell Laboratories, Lucent Technologies, Holmdel, NJ 07733 USA. He is now with Broadcom Corporation, Irvine, CA 92618 USA. K. K. Parhi is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA. Publisher Item Identifier S 1057-7130(98)05058-7.
- Data flow graphs
- High-level synthesis
- Parallel architectures
- Signal processing
- Very large scale integration