Exploiting TLS parallelism at multiple loop-nest levels

Venkatesan Packirisamy, Antonia B Zhai

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

As the number of cores integrated onto a single chip increases, architecture and compiler designers are challenged with the difficulty of utilizing these cores to improve the performance of a single application. Thread-level speculation (TLS) can potentially help by allowing possibly dependent threads to speculatively execute in parallel. Extracting speculative thread from sequential applications is key to efficient TLS execution. Previous work on thread extraction has focused on parallelizing iterations from a single loop-nest level or function continuation. However, the amount of parallelism available at a single loopnest level is sometimes limited, and we are forced to look for parallelism across multiple loop-nest levels. In this paper we propose SpecOPTAL - a compiler algorithm that statically allocates cores to threads extracted from different levels of loopnests. We show that, a subset of SPEC 2006 benchmarks are able to benefit from the proposed technique.

Original languageEnglish (US)
Title of host publicationICPADS '09 - 15th International Conference on Parallel and Distributed Systems
Pages205-212
Number of pages8
DOIs
StatePublished - Dec 1 2009
Event15th International Conference on Parallel and Distributed Systems, ICPADS '09 - Shenzhen, Guangdong, China
Duration: Dec 8 2009Dec 11 2009

Publication series

NameProceedings of the International Conference on Parallel and Distributed Systems - ICPADS
ISSN (Print)1521-9097

Other

Other15th International Conference on Parallel and Distributed Systems, ICPADS '09
CountryChina
CityShenzhen, Guangdong
Period12/8/0912/11/09

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