Exploring fine-grained fault tolerance for nanotechnology devices with the recursive nanobox processor grid

A. J. Kleinosowski; Vasudev V. Pai; Vijay Rangarajan; Priyadarshini Ranganath; Kevin Kleinosowski; Mahesh Subramony; David J. Lilja

doi:10.1109/TNANO.2006.880901

Exploring fine-grained fault tolerance for nanotechnology devices with the recursive nanobox processor grid

A. J. Kleinosowski, Vasudev V. Pai, Vijay Rangarajan, Priyadarshini Ranganath, Kevin Kleinosowski, Mahesh Subramony, David J. Lilja

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

10 Scopus citations

Abstract

Advanced molecular nanotechnology devices are predicted to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS devices. We describe and evaluate the Recursive NanoBox Processor Grid as an application specific, fault-tolerant, parallel computing system designed for fabrication with unreliable nanotechnology devices. In this study we construct hardware description language models of a NanoBox Processor cell and evaluate the effectiveness of our recursive fault masking approach in the presence of random errors. Our analysis shows that complex circuits constructed with encoded lookup tables can operate correctly despite 2% of the nodes being in error. The circuits operate partially correct with up to 4% of the nodes being in error.

Original language	English (US)
Article number	1695958
Pages (from-to)	575-586
Number of pages	12
Journal	IEEE Transactions on Nanotechnology
Volume	5
Issue number	5
DOIs	https://doi.org/10.1109/TNANO.2006.880901
State	Published - Sep 2006

Bibliographical note

Funding Information:
Manuscript received April 17, 2006; revised May 1, 2006. This work was supported in part by IBM, Intel, and Semiconductor Research Corporation under Contract2004-HJ-1190, in part by the National Science Foundation (NSF) under Grant CCR-0210197, in part by the University of Minnesota Digital Technology Center, and in part by the Minnesota Supercomputing Institute. The review of this paper was arranged by Associate Editor W. Porod.

Keywords

Computer architecture
Fault tolerance
Logic design
Nanotechnology
Robustness

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abstract = "Advanced molecular nanotechnology devices are predicted to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS devices. We describe and evaluate the Recursive NanoBox Processor Grid as an application specific, fault-tolerant, parallel computing system designed for fabrication with unreliable nanotechnology devices. In this study we construct hardware description language models of a NanoBox Processor cell and evaluate the effectiveness of our recursive fault masking approach in the presence of random errors. Our analysis shows that complex circuits constructed with encoded lookup tables can operate correctly despite 2% of the nodes being in error. The circuits operate partially correct with up to 4% of the nodes being in error.",

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note = "Funding Information: Manuscript received April 17, 2006; revised May 1, 2006. This work was supported in part by IBM, Intel, and Semiconductor Research Corporation under Contract2004-HJ-1190, in part by the National Science Foundation (NSF) under Grant CCR-0210197, in part by the University of Minnesota Digital Technology Center, and in part by the Minnesota Supercomputing Institute. The review of this paper was arranged by Associate Editor W. Porod.",

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AU - Ranganath, Priyadarshini

AU - Kleinosowski, Kevin

AU - Subramony, Mahesh

AU - Lilja, David J.

N1 - Funding Information: Manuscript received April 17, 2006; revised May 1, 2006. This work was supported in part by IBM, Intel, and Semiconductor Research Corporation under Contract2004-HJ-1190, in part by the National Science Foundation (NSF) under Grant CCR-0210197, in part by the University of Minnesota Digital Technology Center, and in part by the Minnesota Supercomputing Institute. The review of this paper was arranged by Associate Editor W. Porod.

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AB - Advanced molecular nanotechnology devices are predicted to have exceedingly high transient fault rates and large numbers of inherent device defects compared to conventional CMOS devices. We describe and evaluate the Recursive NanoBox Processor Grid as an application specific, fault-tolerant, parallel computing system designed for fabrication with unreliable nanotechnology devices. In this study we construct hardware description language models of a NanoBox Processor cell and evaluate the effectiveness of our recursive fault masking approach in the presence of random errors. Our analysis shows that complex circuits constructed with encoded lookup tables can operate correctly despite 2% of the nodes being in error. The circuits operate partially correct with up to 4% of the nodes being in error.

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KW - Logic design

KW - Nanotechnology

KW - Robustness

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Exploring fine-grained fault tolerance for nanotechnology devices with the recursive nanobox processor grid

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Keywords

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