Exploring subsets of standard cell libraries to exploit natural fault masking capabilities for reliable logic

Drew C. Ness, Christian J. Hescott, David J Lilja

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Deep submicron technology is expected to be plagued by many reliability issues including soft errors in logic. To address this, we demonstrate how exploiting the natural fault masking characteristics of logical functions can be achieved by exploring the design space for selecting subsets of cells from within a cell library prior to synthesis. Subset selection alone is shown to improve the reliability of combinational logic circuits by more than 35%. We compare how subset libraries effect the trade-offs between reliability, area, power, and performance. Further, we show that added benefits of reduced cell library size can benefit the design.

Original languageEnglish (US)
Title of host publicationGLSVLSI'07
Subtitle of host publicationProceedings of the 2007 ACM Great Lakes Symposium on VLSI
Pages208-211
Number of pages4
DOIs
StatePublished - 2007
Event17th Great Lakes Symposium on VLSI, GLSVLSI'07 - Stresa-Lago Maggiore, Italy
Duration: Mar 11 2007Mar 13 2007

Publication series

NameProceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Other

Other17th Great Lakes Symposium on VLSI, GLSVLSI'07
CountryItaly
CityStresa-Lago Maggiore
Period3/11/073/13/07

Keywords

  • Fault masking
  • Fault-tolerance
  • Reliability

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