Fast comparisons of circuit implementations

Shrirang K. Karandikar, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

4 Scopus citations

Abstract

Digital designs can be mapped to different implementations using diverse approaches, with varying cost criteria. Post-processing transforms, such as transistor sizing, can significantly improve circuit performance by optimizing critical paths to meet timing specifications. However, most transistor sizing tools have high execution times, and the possible delay gains due to sizing, and the associated costs are not known prior to sizing. In this paper, we present two metrics for comparing different implementations - the minimum achievable delay and the cost of achieving a target delay - and show how these can be estimated without running a sizing tool. Using these fast and accurate performance estimators, a designer can determine the tradeoffs between multiple functionally identical implementations, and size only the selected implementation.

Original languageEnglish (US)
Pages (from-to)1329-1339
Number of pages11
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume13
Issue number12
DOIs
StatePublished - Dec 2005

Bibliographical note

Funding Information:
Manuscript received April 21, 2005; revised August 5, 2005. This work was supported in part by the National Science Foundation under Award CCR-0205227 and Award CCR-0098117, and by the SRC under Grant 2001-TJ-884. S. K. Karandikar is with the IBM Austin Research Laboratory, Austin, TX 78727 USA (e-mail: akkarand@us.ibm.com). S. S. Sapatnekar is with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA. Digital Object Identifier 10.1109/TVLSI.2005.862727

Keywords

  • Circuit optimization
  • Cost-delay tradeoffs
  • Delay estimation
  • Dynamic programming
  • Gate sizing
  • Logical effort
  • Performance estimation
  • Transistor sizing

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