Fast global gate collapsing technique for high performance designs using static CMOS and pass transistor logic

Yanbin Jiang, Sachin S. Sapatnekar, Cyrus Bamji

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations

Abstract

A new design methodology for mapping circuits is discussed in this paper. It proposes two new techniques for mapping circuits. The first method, known as the odd-level transistor replacement (OTR) method, has a goal that is similar to that of technology mapping, but without the restriction of a fixed library size. The second technique, the Static/PTL method, uses a mix of static CMOS and pass transistor logic (PTL) to realize the circuit, using the relation between PTL and binary decision diagrams. The methods are very efficient and can handle all of the ISCAS85 benchmark circuits in minutes. A comparison of the results with traditional technology mapping using SIS on different libraries shows an average delay reduction about 40% for OTR, and an average delay reduction above 50% for the Static/PTL method.

Original languageEnglish (US)
Title of host publicationVLSI in Computers and Processors
PublisherIEEE
Pages276-281
Number of pages6
StatePublished - Dec 1 1998
EventProceedings of the 1998 IEEE International Conference on Computer Design - Austin, TX, USA
Duration: Oct 5 1998Oct 7 1998

Other

OtherProceedings of the 1998 IEEE International Conference on Computer Design
CityAustin, TX, USA
Period10/5/9810/7/98

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