High level synthesis (HLS) is often employed as a frequently called kernel in design space exploration (DSE). Therefore, its nontrivial runtime becomes a bottleneck that prevents extensive solution search in DSE. In this work, we develop a mapping-based HLS technique that is fast and friendly to local incremental changes. It exploits the static-single assignment (SSA)-form intermediate representation (IR), starts with direct mapping from the IR to a fully pipelined circuit and performs incremental resource sharing in an iterative manner, which then alters the fully pipelined circuit to a partially pipelined or nonpipelined circuit. An algorithm is also proposed for automatic synthesis of pipeline interlocks to avoid structural hazards incurred by resource conflicts. Experimental results show that the proposed method is fast without loss of circuit performance in terms of throughput.
|Original language||English (US)|
|Title of host publication||Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019|
|Publisher||IEEE Computer Society|
|Number of pages||6|
|State||Published - Apr 23 2019|
|Event||20th International Symposium on Quality Electronic Design, ISQED 2019 - Santa Clara, United States|
Duration: Mar 6 2019 → Mar 7 2019
|Name||Proceedings - International Symposium on Quality Electronic Design, ISQED|
|Conference||20th International Symposium on Quality Electronic Design, ISQED 2019|
|Period||3/6/19 → 3/7/19|
Bibliographical noteFunding Information:
work is partially supported by NSF (CCF-1525749,CCF-1525925).
This work is partially supported by NSF (CCF-1525749,CCF-1525925).
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