Fast scheduling and placement methods for C to hardware/software compilation

Kia Bazargan, Majid Sarrafzadeh

Research output: Contribution to journalArticlepeer-review

1 Scopus citations

Abstract

Advances in the FPGA technology, both in terms of device capacity and architecture, have resulted in introduction of reconfigurable computing machines, where the hardware adapts itself to the running application to gain speedup. To keep up with the ever-growing performance expectations of such systems, designers need new methodologies and tools for developing reconfigurable computing systems (RCS). This paper addresses the need for fast compilation and physical design phase to be used in application development/debugging/testing cycle for RCS. We present a high-level synthesis approach that is integrated with placement, hence making the compilation cycle much faster. On the average, our tool generates the VHDL code (and the corresponding placement information) from the data flow graph of a program in less than a minute. By losing 1.3 times in the quality of the design, we can achieve, 10.7 times speedup in the Xilinx placement phase, and 2.5 times overall speedup in the Xilinx place-and-route phase.

Original languageEnglish (US)
Pages (from-to)57-68
Number of pages12
JournalProceedings of SPIE - The International Society for Optical Engineering
Volume4212
Issue number1
DOIs
StatePublished - Oct 6 2000

Keywords

  • Compilation
  • Design Automation
  • High-level Synthesis
  • Physical Design
  • Recnfigurable Computing System

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