Physical unclonable functions (PUFs) can be used to generate unique signatures of integrated circuit (IC) chips. XOR arbiter PUFs (XOR PUFs), that typically contain multiple standard arbiter PUFs as their components, are more secure than standard arbiter PUFs. This paper proposes design of feed-forward XOR PUFs (FFXOR PUFs) where each component PUF is a feed-forward arbiter PUF (FF PUF). Arbiter PUFs suffer from two main drawbacks: vulnerability to modeling attacks and degraded reliability. It is shown that FFXOR PUFs cannot be accurately modeled if the number of component PUFs is more than 5 or 6. We also state that the number of machine learning runs required to learn a model using evolutionary strategies increases by a factor of N^2/2 if N-stage FF PUFs with one loop are used as components instead of standard arbiter PUFs. In general, for FF PUFs with k loops (one intermediate arbiter), it would increase by a factor of N\choose k+1. We also show that the use of a thresholding strategy can increase the reliability of FFXOR PUFs by about 30% for a 15% noise level.
|Original language||English (US)|
|Title of host publication||GLSVLSI 2019 - Proceedings of the 2019 Great Lakes Symposium on VLSI|
|Publisher||Association for Computing Machinery|
|Number of pages||4|
|State||Published - May 13 2019|
|Event||29th Great Lakes Symposium on VLSI, GLSVLSI 2019 - Tysons Corner, United States|
Duration: May 9 2019 → May 11 2019
|Name||Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI|
|Conference||29th Great Lakes Symposium on VLSI, GLSVLSI 2019|
|Period||5/9/19 → 5/11/19|
Bibliographical noteFunding Information:
This research has been supported by the National Science Foundation under grant number CNS-1441639 and the Semiconductor Research Corporation under contract number 2014-TS-2560.
© 2019 ACM.
- Artificial neural network
- Feed-forward XOR puf
- Feed-forward puf
- Hardware security
- XOR puf