FEMTO: Fast error analysis in Multipliers through Topological Traversal

Deepashree Sengupta, Sachin S. Sapatnekar

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

Approximate computing has emerged as a circuit design technique that can reduce system power without significantly sacrificing the output quality in error-resilient applications. However, there are few approaches for systematically and efficiently determining the error introduced by approximate hardware units. This paper focuses on the development of error analysis techniques for approximate multipliers, which are a key hardware component used in error-resilient applications, and presents a novel algorithm that efficiently determines the probability distribution of the error introduced by the approximation. The accuracy of the technique is demonstrated to be comparable to Monte Carlo simulations, while being significantly less computationally intensive.

Original languageEnglish (US)
Title of host publication2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages294-299
Number of pages6
ISBN (Electronic)9781467383882
DOIs
StatePublished - Jan 5 2016
Event34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 - Austin, United States
Duration: Nov 2 2015Nov 6 2015

Publication series

Name2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015

Other

Other34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015
CountryUnited States
CityAustin
Period11/2/1511/6/15

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