FEMTO: Fast error analysis in Multipliers through Topological Traversal

Deepashree Sengupta; Sachin S. Sapatnekar

doi:10.1109/ICCAD.2015.7372583

FEMTO: Fast error analysis in Multipliers through Topological Traversal

Deepashree Sengupta, Sachin S. Sapatnekar

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

12 Scopus citations

Abstract

Approximate computing has emerged as a circuit design technique that can reduce system power without significantly sacrificing the output quality in error-resilient applications. However, there are few approaches for systematically and efficiently determining the error introduced by approximate hardware units. This paper focuses on the development of error analysis techniques for approximate multipliers, which are a key hardware component used in error-resilient applications, and presents a novel algorithm that efficiently determines the probability distribution of the error introduced by the approximation. The accuracy of the technique is demonstrated to be comparable to Monte Carlo simulations, while being significantly less computationally intensive.

Original language	English (US)
Title of host publication	2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	294-299
Number of pages	6
ISBN (Electronic)	9781467383882
DOIs	https://doi.org/10.1109/ICCAD.2015.7372583
State	Published - Jan 5 2016
Event	34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 - Austin, United States Duration: Nov 2 2015 → Nov 6 2015

Publication series

Name	2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015

Other

Other	34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015
Country/Territory	United States
City	Austin
Period	11/2/15 → 11/6/15

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

Access

10.1109/ICCAD.2015.7372583

OpenUrl availability

Full text

Cite this

Sengupta, D., & Sapatnekar, S. S. (2016). FEMTO: Fast error analysis in Multipliers through Topological Traversal. In 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 (pp. 294-299). Article 7372583 (2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICCAD.2015.7372583

FEMTO: Fast error analysis in Multipliers through Topological Traversal. / Sengupta, Deepashree; Sapatnekar, Sachin S.
2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc., 2016. p. 294-299 7372583 (2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Sengupta, D & Sapatnekar, SS 2016, FEMTO: Fast error analysis in Multipliers through Topological Traversal. in 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015., 7372583, 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015, Institute of Electrical and Electronics Engineers Inc., pp. 294-299, 34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015, Austin, United States, 11/2/15. https://doi.org/10.1109/ICCAD.2015.7372583

Sengupta D, Sapatnekar SS. FEMTO: Fast error analysis in Multipliers through Topological Traversal. In 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015. Institute of Electrical and Electronics Engineers Inc. 2016. p. 294-299. 7372583. (2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015). doi: 10.1109/ICCAD.2015.7372583

@inproceedings{32d3d6c3f08c41e5b86c387c5e676236,

title = "FEMTO: Fast error analysis in Multipliers through Topological Traversal",

abstract = "Approximate computing has emerged as a circuit design technique that can reduce system power without significantly sacrificing the output quality in error-resilient applications. However, there are few approaches for systematically and efficiently determining the error introduced by approximate hardware units. This paper focuses on the development of error analysis techniques for approximate multipliers, which are a key hardware component used in error-resilient applications, and presents a novel algorithm that efficiently determines the probability distribution of the error introduced by the approximation. The accuracy of the technique is demonstrated to be comparable to Monte Carlo simulations, while being significantly less computationally intensive.",

author = "Deepashree Sengupta and Sapatnekar, {Sachin S.}",

note = "Publisher Copyright: {\textcopyright} 2015 IEEE.; 34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015 ; Conference date: 02-11-2015 Through 06-11-2015",

year = "2016",

month = jan,

day = "5",

doi = "10.1109/ICCAD.2015.7372583",

language = "English (US)",

series = "2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "294--299",

booktitle = "2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015",

}

TY - GEN

T1 - FEMTO

T2 - 34th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015

AU - Sengupta, Deepashree

AU - Sapatnekar, Sachin S.

PY - 2016/1/5

Y1 - 2016/1/5

N2 - Approximate computing has emerged as a circuit design technique that can reduce system power without significantly sacrificing the output quality in error-resilient applications. However, there are few approaches for systematically and efficiently determining the error introduced by approximate hardware units. This paper focuses on the development of error analysis techniques for approximate multipliers, which are a key hardware component used in error-resilient applications, and presents a novel algorithm that efficiently determines the probability distribution of the error introduced by the approximation. The accuracy of the technique is demonstrated to be comparable to Monte Carlo simulations, while being significantly less computationally intensive.

AB - Approximate computing has emerged as a circuit design technique that can reduce system power without significantly sacrificing the output quality in error-resilient applications. However, there are few approaches for systematically and efficiently determining the error introduced by approximate hardware units. This paper focuses on the development of error analysis techniques for approximate multipliers, which are a key hardware component used in error-resilient applications, and presents a novel algorithm that efficiently determines the probability distribution of the error introduced by the approximation. The accuracy of the technique is demonstrated to be comparable to Monte Carlo simulations, while being significantly less computationally intensive.

UR - http://www.scopus.com/inward/record.url?scp=84964459859&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84964459859&partnerID=8YFLogxK

U2 - 10.1109/ICCAD.2015.7372583

DO - 10.1109/ICCAD.2015.7372583

M3 - Conference contribution

AN - SCOPUS:84964459859

T3 - 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015

SP - 294

EP - 299

BT - 2015 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015

PB - Institute of Electrical and Electronics Engineers Inc.

Y2 - 2 November 2015 through 6 November 2015

ER -

FEMTO: Fast error analysis in Multipliers through Topological Traversal

Abstract

Publication series

Other

Bibliographical note

Access

OpenUrl availability

Other files and links

Fingerprint

Cite this