## Abstract

This paper presents the architecture and implementation of a full-custom 1.2 micron CMOS VLSI chip that executes a shared division/square root algorithm operating on mantissas (23-b in length) of single precision IEEE 754 std. floating point numbers. The division and square root algorithms used in this implementation are the radix 2 signed digit based digit-by-digit schemes. These two algorithms perform quotient/root digit selection using two most-significant digits of the partial remainder and are hence faster than other similar previously proposed radix 2 shared division/square root schemes. This chip runs at a clock rate of about 66MHz at 5.0V (from simulations) and requires 29 cycles per divide/square root operation from the time the operands are provided at its pin inputs.

Original language | English (US) |
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Title of host publication | Proceedings - IEEE International Conference on Computer Design |

Subtitle of host publication | VLSI in Computers and Processors |

Editors | Anon |

Publisher | IEEE |

Pages | 472-478 |

Number of pages | 7 |

State | Published - Dec 1 1995 |

Event | Proceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Austin, TX, USA Duration: Oct 2 1995 → Oct 4 1995 |

### Other

Other | Proceedings of the 1995 IEEE International Conference on Computer Design: VLSI in Computers & Processors |
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City | Austin, TX, USA |

Period | 10/2/95 → 10/4/95 |