Floorplan optimization on multiprocessors

Sunil Arvindam, Vipin Kumar, V. Nageshwara Rao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

14 Scopus citations

Abstract

A parallel formulation of a branch-and-bound algorithm for floorplan optimization in VLSI design is given. Implementation details and performance analyses of the authors' formulation are presented. This implementation was done on a 128-node Symult s2010 multicomputer, as well as on a network of 16 SUN workstations. In the experiments with realistic problems, linear speedups on both machine configurations were obtained. Previous analyses of a similar parallel algorithm suggest that linear speedup can be obtained even on very large computers (>1000 processors) on practical instances of this problem.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors
Editors Anon
PublisherPubl by IEEE
Pages109-114
Number of pages6
StatePublished - Dec 1 1989
EventProceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA
Duration: Oct 2 1989Oct 4 1989

Other

OtherProceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors
CityCambridge, MA, USA
Period10/2/8910/4/89

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