FPC: A floating-point processor controller chip for systolic signal processing

Ross Smith, Gerald Sobelman, George Luk, Koichi Suda, Jeff Bracken

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

The FPC (floating-point process controller) chip design and the AMD Am29325 32-b floating-point processor mathematics chip form a two-chip cell designed for one- or two-dimensional systolic arrays which can be used to implement a wide variety of signal processing applications. The FPC controls the Am29325, routes data to and from it, and routes data and control to other cells in the array. Unique features include two interchangeable data memories, an input port which can be used as either a local or global port, and a 32-b instruction word that provides concurrent use of all cell resources. Additional features include a program memory, two data streams, and three control streams. The novel architectural features of the cell are described, and a matrix multiplication example is used to demonstrate their usefulness.

Original languageEnglish (US)
Title of host publicationProceedings - IEEE International Conference on Computer Design
Subtitle of host publicationVLSI in Computers and Processors
Editors Anon
PublisherPubl by IEEE
Pages14-17
Number of pages4
StatePublished - Dec 1 1989
EventProceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA
Duration: Oct 2 1989Oct 4 1989

Other

OtherProceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors
CityCambridge, MA, USA
Period10/2/8910/4/89

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