Abstract
The FPC (floating-point process controller) chip design and the AMD Am29325 32-b floating-point processor mathematics chip form a two-chip cell designed for one- or two-dimensional systolic arrays which can be used to implement a wide variety of signal processing applications. The FPC controls the Am29325, routes data to and from it, and routes data and control to other cells in the array. Unique features include two interchangeable data memories, an input port which can be used as either a local or global port, and a 32-b instruction word that provides concurrent use of all cell resources. Additional features include a program memory, two data streams, and three control streams. The novel architectural features of the cell are described, and a matrix multiplication example is used to demonstrate their usefulness.
Original language | English (US) |
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Title of host publication | Proceedings - IEEE International Conference on Computer Design |
Subtitle of host publication | VLSI in Computers and Processors |
Editors | Anon |
Publisher | Publ by IEEE |
Pages | 14-17 |
Number of pages | 4 |
State | Published - Dec 1 1989 |
Event | Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors - Cambridge, MA, USA Duration: Oct 2 1989 → Oct 4 1989 |
Other
Other | Proceedings - 1989 IEEE International Conference on Computer Design: VLSI in Computers & Processors |
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City | Cambridge, MA, USA |
Period | 10/2/89 → 10/4/89 |