Frequency-hopped quadrature frequency synthesizer in 0.13-μm technology

Narasimha R. Lanka; Satwik A. Patnaik; Ramesh A. Harjani

doi:10.1109/JSSC.2011.2139490

Frequency-hopped quadrature frequency synthesizer in 0.13-μm technology

Narasimha R. Lanka, Satwik A. Patnaik, Ramesh A. Harjani

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

26 Scopus citations

Abstract

This paper presents a Wireless-USB/WiMedia-compliant fast-hopping frequency synthesizer architecture with quadrature outputs based on sub-harmonic injection-locking. The synthesizer features a cross-coupled quadrature digitally-controlled oscillator, that is injection-locked to a sub-harmonic frequency. An intuitive closed-form expression for the dynamics of the quadrature injection-locked oscillator and a technique to achieve fast frequency-hopping, are presented. The overall architecture, based on this technique, is a CMOS-only implementation and has been fabricated in a 0.13-μ m SiGe BiCMOS process. On-chip mixers have been implemented to measure the quadrature accuracy of the outputs. Measurement results indicate lock-times of less than 2.5 ns, a locked phase noise of -114 dBc/Hz at 1 MHz offset and a quadrature accuracy of better than 0.5°. The frequency synthesizer (excluding output buffers) occupies an area of 0.27 mm² and consumes 14.5 mW of power. The best and worst case spur suppression achieved are 47 and 31 dB, respectively. This is the lowest power fast-hopping quadrature frequency synthesizer that has been reported to date.

Original language	English (US)
Article number	5766062
Pages (from-to)	2021-2032
Number of pages	12
Journal	IEEE Journal of Solid-State Circuits
Volume	46
Issue number	9
DOIs	https://doi.org/10.1109/JSSC.2011.2139490
State	Published - Sep 2011

Bibliographical note

Funding Information:
Manuscript received October 22, 2010; revised February 15, 2011; accepted March 25, 2011. Date of publication May 12, 2011; date of current version August 24, 2011. This paper was approved by Associate Editor Kunihiko Iizuka. This work was supported in part by a grant from Semiconductor Research Corporation. N. R. Lanka was with the University of Minnesota, Minneapolis, MN 55455 USA. He is now with Intel Corporation, Santa Clara, CA 95054 USA. S. A. Patnaik was with the University of Minnesota, Minneapolis, MN 55455 USA. He is now with Intel Corporation, Hillsboro, OR 97124 USA. R. A. Harjani is with the University of Minnesota, Minneapolis, MN 55455 USA (e-mail: harjani@ece.umn.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2011.2139490

Copyright:
Copyright 2011 Elsevier B.V., All rights reserved.

Keywords

Adler's equation
Colpitts oscillator
Injection locking
fast-hopping
fast-locking
frequency settling
frequency-hopped spread spectrum (FHSS)
frequency-shift keying (FSK)
fundamental locking
harmonic locking
injection-locked oscillator (ILO)
lock acquisition
transient behavior
ultra-wide-band (UWB)

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title = "Frequency-hopped quadrature frequency synthesizer in 0.13-μm technology",

abstract = "This paper presents a Wireless-USB/WiMedia-compliant fast-hopping frequency synthesizer architecture with quadrature outputs based on sub-harmonic injection-locking. The synthesizer features a cross-coupled quadrature digitally-controlled oscillator, that is injection-locked to a sub-harmonic frequency. An intuitive closed-form expression for the dynamics of the quadrature injection-locked oscillator and a technique to achieve fast frequency-hopping, are presented. The overall architecture, based on this technique, is a CMOS-only implementation and has been fabricated in a 0.13-μ m SiGe BiCMOS process. On-chip mixers have been implemented to measure the quadrature accuracy of the outputs. Measurement results indicate lock-times of less than 2.5 ns, a locked phase noise of -114 dBc/Hz at 1 MHz offset and a quadrature accuracy of better than 0.5°. The frequency synthesizer (excluding output buffers) occupies an area of 0.27 mm2 and consumes 14.5 mW of power. The best and worst case spur suppression achieved are 47 and 31 dB, respectively. This is the lowest power fast-hopping quadrature frequency synthesizer that has been reported to date.",

keywords = "Adler's equation, Colpitts oscillator, Injection locking, fast-hopping, fast-locking, frequency settling, frequency-hopped spread spectrum (FHSS), frequency-shift keying (FSK), fundamental locking, harmonic locking, injection-locked oscillator (ILO), lock acquisition, transient behavior, ultra-wide-band (UWB)",

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note = "Funding Information: Manuscript received October 22, 2010; revised February 15, 2011; accepted March 25, 2011. Date of publication May 12, 2011; date of current version August 24, 2011. This paper was approved by Associate Editor Kunihiko Iizuka. This work was supported in part by a grant from Semiconductor Research Corporation. N. R. Lanka was with the University of Minnesota, Minneapolis, MN 55455 USA. He is now with Intel Corporation, Santa Clara, CA 95054 USA. S. A. Patnaik was with the University of Minnesota, Minneapolis, MN 55455 USA. He is now with Intel Corporation, Hillsboro, OR 97124 USA. R. A. Harjani is with the University of Minnesota, Minneapolis, MN 55455 USA (e-mail: harjani@ece.umn.edu). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2011.2139490 Copyright: Copyright 2011 Elsevier B.V., All rights reserved.",

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AB - This paper presents a Wireless-USB/WiMedia-compliant fast-hopping frequency synthesizer architecture with quadrature outputs based on sub-harmonic injection-locking. The synthesizer features a cross-coupled quadrature digitally-controlled oscillator, that is injection-locked to a sub-harmonic frequency. An intuitive closed-form expression for the dynamics of the quadrature injection-locked oscillator and a technique to achieve fast frequency-hopping, are presented. The overall architecture, based on this technique, is a CMOS-only implementation and has been fabricated in a 0.13-μ m SiGe BiCMOS process. On-chip mixers have been implemented to measure the quadrature accuracy of the outputs. Measurement results indicate lock-times of less than 2.5 ns, a locked phase noise of -114 dBc/Hz at 1 MHz offset and a quadrature accuracy of better than 0.5°. The frequency synthesizer (excluding output buffers) occupies an area of 0.27 mm2 and consumes 14.5 mW of power. The best and worst case spur suppression achieved are 47 and 31 dB, respectively. This is the lowest power fast-hopping quadrature frequency synthesizer that has been reported to date.

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KW - harmonic locking

KW - injection-locked oscillator (ILO)

KW - lock acquisition

KW - transient behavior

KW - ultra-wide-band (UWB)

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Frequency-hopped quadrature frequency synthesizer in 0.13-μm technology

Abstract

Bibliographical note

Keywords

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